External Links

    Journal: Integration

    Volume 7, Issue 3

    211 -- 0Lambert Spaanenburg. Editorial
    213 -- 230Reiner Kolla, Paul Molitor. A note on hierarchical layer-assignment
    231 -- 245Yue-Sun Kuo, T. C. Chern, Wei Kuan Shih. Fast algorithm for optimal layer assignment
    247 -- 266Jeffrey J. Joyce. Formal specification and verification of microprocessor systems
    267 -- 281Sudipta Bhawmik, V. K. Narang, Parimal Pal Chaudhuri. Selecting test methodologies for PLAs and random logic modules in VLSI circuits - an expert systems approach
    283 -- 302C. P. Ravikumar, Sarma Sastry. A hardware accelerator for hierarchical VLSI routing
    303 -- 324Alaaeldin A. M. Amin, Kent F. Smith. Test generation and fault detection for VLSI PPL circuits
    325 -- 0Sharad C. Seth, Vishwani D. Agrawal. A new model for computation of probabilistic testability in combinational circuits

    Volume 7, Issue 2

    101 -- 0Lambert Spaanenburg. Editorial
    103 -- 125Lionel M. Ni, Youran Lan, Abdol-Hossein Esfahanian. A VLSI router design for hypercube multiprocessors
    127 -- 149Francesco Curatelli, P. Antognetti. A reconfigurable wiring algorithm for three-layer maze routing
    151 -- 187Richard J. Enbody, David H. C. Du. SPYDER: a serial/parallel goal-directed router
    189 -- 201Thomas R. Mueller, D. F. Wong, C. L. Liu. An enhanced bottom-up algorithm for floorplan design

    Volume 7, Issue 1

    0 -- 0Lambert Spaanenburg. Editorial
    1 -- 20Jer Min Jou, Jau-Yien Lee. A new 3-layer rectilinear area router with obstacle avoidance
    21 -- 34Sun Young Hwang. Incremental algorithms for digital simulation
    35 -- 48Hartmut Grabinski. An algorithm for computing the signal propagation on lossy VLSI interconnect systems in the time domain
    49 -- 75Sharad C. Seth, Vishwani D. Agrawal. A new model for computation of probabilistic testability in combinational circuits
    77 -- 91P. K. Lim, Maher A. Sid-Ahmed, Graham A. Jullien. VLSI implementation of a digital image threshold selection architecture
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