External Links

    Journal: Integration

    Volume 8, Issue 3

    207 -- 0Lambert Spaanenburg. Editorial
    209 -- 247Ganesh Gopalakrishnan, Richard M. Fujimoto, Venkatesh Akella, Narayana Mani. HOP: A process model for synchronous hardware; semantics and experiments in process composition
    249 -- 268Chidchanok Lursinsap, Daniel Gajski. Power routing in channelless floorplan layouts
    269 -- 283F. Lombardi. On a new class of C-testable systolic arrays
    285 -- 300Anucha Pitaksanonkul, Suchai Thanawastien, Chidchanok Lursinsap. Bisection trees and half-quad trees: Memory and time efficient data structures for VLSI layout editors
    301 -- 320Brian C. McKinney, Fayez El Guibaly. VLSI design of an FFT processor network
    321 -- 330G. E. A. Lousberg. Two terminal channel routing using at most density plus two tracks
    331 -- 340Chein-Wei Jen, Ding-Ming Kwai. Multi-dimensional parallel computing structures for regular iterative algorithms
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