| 97 | -- | 0 | Lambert Spannenburg. Editorial |
| 99 | -- | 109 | Bruno Rouzeyre, Toufic Ezzedine, Georges Sagnes. Operators allocation in the silicon compiler SCOOP |
| 111 | -- | 141 | Teofilo F. Gonzalez, Si-Qing Zheng. Stretching and three-layer wiring planar layouts |
| 143 | -- | 153 | Elena Lodi, Fabrizio Luccio, Linda Pagli. Channel routing for strictly multiterminal nets |
| 155 | -- | 172 | Peter D. Hortensius, Howard C. Card, Robert D. McLeod. VLSI computing architectures for Ising model simulation |
| 173 | -- | 187 | Luc J. M. Claesen, J. P. Schupp, P. Das, P. Johannes, S. Perremans, Hugo De Man. Efficient false path elimination algorithms for timing verification by event graph preprocessing |
| 189 | -- | 199 | Kenneth J. Schultz, David H. K. Hoe, C. Andre T. Salama. A microprogrammable processor using single poly EPROM |