| 137 | -- | 139 | Sandro Bartolini, Roberto Giorgi. Issues in Embedded Single-Chip Multicore Architectures |
| 141 | -- | 155 | David Ródenas, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, George Almási, Calin Cascaval, José G. Castaños, José E. Moreira. Exploiting multilevel parallelism using OpenMP on a massive multithreaded architecture |
| 157 | -- | 166 | John Oliver, Ravishankar Rao, Diana Franklin, Frederic T. Chong, Venkatesh Akella. Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications |
| 167 | -- | 179 | Hamed Fatemi, Bart Mesman, Henk Corporaal, Twan Basten, Richard P. Kleihorst. RC-SIMD: Reconfigurable communication SIMD architecture for image processing applications |
| 181 | -- | 190 | Pei Gu, Uzi Vishkin. Case study of gate-level logic simulation on an extremely fine-grained chip multiprocessor |
| 191 | -- | 205 | Ben A. Abderazek, Sotaro Kawata, Masahiro Sowa. Design and architecture for an embedded 32-bit QueueCore |
| 207 | -- | 219 | Afrin Naz, Krishna M. Kavi, Wentong Li, Philip H. Sweany. Tiny split data-caches make big performance impact for embedded applications |
| 221 | -- | 233 | Alex Settle, Dan Connors, Enric Gibert, Antonio González. A dynamically reconfigurable cache for multithreaded processors |
| 235 | -- | 247 | Patrick Anthony La Fratta, James M. Baker Jr.. Exploring power reduction options for a single-chip multiprocessor through system-level modeling |
| 249 | -- | 260 | Haakon Dybdahl, Per Gunnar Kjeldsberg, Marius Grannæs, Lasse Natvig. Destructive-read in embedded DRAM, impact on power consumption |
| 261 | -- | 269 | Yul Chu, Arul Sandeep Gade, Abhishek Bhaduri. A low-power cache scheme for embedded computing |