| 0 | -- | 0 | Lutz Richter. Chairman's introduction |
| 1 | -- | 0 | Lutz Richter. Opening and keynote session |
| 3 | -- | 8 | Niklaus Wirth. Oberon: A system for workstations |
| 9 | -- | 0 | Hubert Huschke. Communications strategies in international banking |
| 11 | -- | 13 | Hubert Huschke. Communication strategies in international banking |
| 15 | -- | 0 | Joseph A. Fisher. Microprogramming, microprocessing and supercomputing |
| 17 | -- | 20 | Joseph A. Fisher. Microprogramming, microprocessing and supercomputing |
| 21 | -- | 0 | Helmut Painke. Microelectronics: the VLSI-/370 microprocessor I |
| 23 | -- | 27 | Helmut Painke. VLSI-/370 microprocessor overview |
| 29 | -- | 33 | Helmut Schettler. VLSI-/370 microprocessor chip technology |
| 35 | -- | 42 | Wolfgang Roesner. The logic design language and verification environment for the VLSI-/370 |
| 43 | -- | 47 | Bernhard Kick. Logic synthesis in the design of the VLSI-/370 microprocessor |
| 49 | -- | 0 | John Mølgaard. Software engineering: System aspects |
| 51 | -- | 55 | Antti Auer, Pekka Kemppainen, Ari Okkonen, Veikko Seppänen. Automated code generation of embedded real-time systems |
| 57 | -- | 62 | Massimo Ancona, Andrea Clematis, Vittoria Gianuzzi. Two language levels for system programming |
| 63 | -- | 70 | Fausto Distante, Donatella Sciuto. Behavioral testing of multilevel system software |
| 73 | -- | 78 | Friedrich Mayer-Lindenberg. Practical multiprocessor and realtime programming in the fifth programming environment |
| 79 | -- | 84 | Dharma P. Agrawal, Jon Mauney, L. Taylor Simpson. Structure of a parallelizing compiler for the B-HIVE multicomputer |
| 85 | -- | 92 | Massimo Ancona, T. Bottino, Andrea Clematis, Gabriella Dodero, Vittoria Gianuzzi, L. Pareto, M. Pronzato, A. Repetti. LINDA: An allocator for embedded multiprocessor systems |
| 95 | -- | 102 | Yehuda Wallach, E. Yaprak. Use of local-area networks as alternating sequential-parallel systems |
| 103 | -- | 110 | Michel N. X. Dang, Christophe Diot, I. Sabouni, L. Sponga. Specific data structure intended for the implementation of high level ISO standards: Associated algorithms and dedicated hardware |
| 111 | -- | 119 | Patrick M. J. Hellemans, Hubert J. M. Decuypere. Automatic protocol generation based on x.409 specifications |
| 121 | -- | 0 | Harald Schumny. Short notes I |
| 125 | -- | 129 | Siegfried Heinkele. Timing verification for the VLSI-/370 microprocessor |
| 131 | -- | 135 | Uwe Schulz. Hierarchical physical design system for VLSI-/370 microprocessor |
| 137 | -- | 145 | Harald Gerst. Verification of the VLSI-/370 microprocessor |
| 149 | -- | 152 | Erik F. Dirkx, Jacques Tiberghien. An animated simulation environment for microprocessors |
| 153 | -- | 159 | Thomas Bemmerl, Norbert Erl, Olav Hansen. Menu and graphic driven human interfaces for high level debuggers |
| 161 | -- | 165 | Malcolm Verrall. PCTE - The kernel of software engineering environments |
| 169 | -- | 177 | Kevin Murray, Andy J. Wellings. Issues in the design and implementation of a distributed operating system for a network of transputers |
| 179 | -- | 185 | Herman Moons, Pierre Verbaeten. Software development in server-oriented systems the HERMIX approach |
| 187 | -- | 193 | Yolande Berbers, Pierre Verbaeten. Design of the Hermix distributed operating system: Structural aspects |
| 197 | -- | 204 | Philippe O. A. Navaux, Paulo Fernandes, Maurizio Tazza. SARA: A processor interconnection performance analysis tool |
| 205 | -- | 207 | Gert Van Der Jeugt, Erik F. Dirkx, Jacques Tiberghien. Protocol description and simulation in the OCCAM programming language |
| 213 | -- | 218 | Francesco Curatelli, Giacomo M. Bisio, Giovanni Borghero, Ermanno Di Zitti. A behavioural simulator and its use for the validation of hypercube architectures |
| 219 | -- | 226 | Raivo Raud. A language environment for asic design |
| 227 | -- | 232 | Jozef A. De Man. Designing digital systems with a function language |
| 233 | -- | 238 | C. Matthäus, B. Krüger-Sprengel, C. Glowacz, Uwe Hübner, Heinrich Theodor Vierhaus. CMOS fault modeling, test generation and design for testability |
| 241 | -- | 248 | Steven T. Krolak, Valentin Antipa. DEOS - A dynamically extendible object-oriented system |
| 249 | -- | 255 | Louis Marinos, Mike P. Papazoglou. Enhancing intermodel transformations in a distributed object-oriented database system |
| 257 | -- | 265 | Klaus W. Pleßmann, L. Tassakos. Concurrent, object-oriented program design in real-time systems |
| 267 | -- | 272 | Dimitris N. Christodoulakis. Petri net semantics of smalltalk-80 |
| 273 | -- | 0 | Jacques Tiberghien. Parallel processing: Transputers I |
| 275 | -- | 279 | P. Knoppers, Ad J. Van de Goor, O. M. Gunhildsbu, P. Stravers. Transputer network with flexible topology |
| 281 | -- | 289 | Pradip K. Das, D. Q. M. Fay. Performance studies of multi-transputer architectures with static and dynamic links |
| 291 | -- | 298 | Winfried Hahn, H. Anger, Andreas Hagerer, B. Schuster. A multi-transputer-net as a hardware simulation environment |
| 299 | -- | 305 | Franz J. Rammig, Martin Schrewe, Gerhard Vorloeper. A transputer-based accelerator for multilevel digital simulation |
| 307 | -- | 0 | Ferenc Vajda. Applications: Image and speech processing |
| 309 | -- | 314 | A. D. Houghton, N. L. Seed. A computer architecture for real time image processing using VLSI |
| 315 | -- | 324 | P. Fernin, Stephen C. Winter, Derek R. Wilson, H. Reignier. Implementation of an intelligent SAR image registration system |
| 325 | -- | 333 | Ad J. Van de Goor, G. J. Nanninga. Speech synthesis system with unlimited vocabulary for the Dutch language |
| 335 | -- | 0 | Harald Schumny. Short notes II |
| 337 | -- | 0 | Reiner W. Hartenstein. Microelectronics: VLSI design tools I |
| 339 | -- | 346 | A. Fox, C. T. Spracklen, C. P. Jolly. Logic synthesis with constraints |
| 347 | -- | 352 | Zebo Peng. Let's design asynchronous VLSI systems |
| 353 | -- | 359 | Anna Antola. Evaluation of complexity for different layouts of butterfly networks |
| 361 | -- | 0 | Josef de Man. Session D2: Software engineering: Formal methods I |
| 363 | -- | 370 | Ingo Eichenseher, Theo Ungerer, Eberhard Zehendner. CADL - A formal description language for parallel computer architectures |
| 371 | -- | 378 | Jeffrey J. Joyce. Formal specification and verification of microprocessor systems |
| 379 | -- | 385 | Bjarne Gertz Pedersen. Design of real time systems. - A method and a tool |
| 389 | -- | 396 | O. Boudillet, Stephen C. Winter, Derek R. Wilson. The implementation of a functional machine on a transputer network |
| 397 | -- | 402 | Kenneth Adamson, G. Donnan, Norman D. Black. Simple transformation rules in the application of transputers to the physiological processing of speech |
| 403 | -- | 408 | Mark B. Sandler, Shirin Eghtesadi. Transputer based implementations of the hough transform for computer vision |
| 409 | -- | 0 | John Billingsley. Applications: Sensors and robotics |
| 411 | -- | 418 | Ralf Hinkel, Thomas Knieriemen, Ewald von Puttkamer. A rotating laser range finder and attached data interpretation for use in an autonomous mobile robot |
| 419 | -- | 423 | Bing Lam Luk, Fazel Naghdy, John Billingsley. Stochastic force sensing application in robotics |
| 425 | -- | 431 | H. Guiheux, C. Mardapittas, Derek R. Wilson, Stephen C. Winter. A model based recognition system for tactile data |
| 433 | -- | 0 | Jan Wilmink. Computer music I |
| 435 | -- | 441 | Goffredo Haus. Music processing at L.I.M |
| 443 | -- | 446 | Fiorella Terenzi. The computer audio research laboratory at the center for music experiment and related research |
| 449 | -- | 454 | Timo Juntunen, Jorma Kivelä, Auli Reinikka, Matti Sipola, Juha-Pekka Soininen, Kari Tiensyrjä, Tuomo Tikkanen. Real-time structured analysis in system level design of embedded ASICs |
| 455 | -- | 460 | Tore Sæter. Software techniques for integrating text and graphics in VLSI CAD tools |
| 461 | -- | 468 | Rainer Buschke, Klaus Lagemann. Error retracing and fault localization techniques within Simueva, a system for evaluation of simulation results |
| 471 | -- | 482 | Volker Gruhn, Matthias Hallmann. A Petri Net based compiler for the prototyping language RELOS |
| 483 | -- | 490 | G. León, S. Marchena. Formal conversion between LOTOS specification and Galileo nets |
| 491 | -- | 500 | H. Zedan. On the analysis of occam real-time distributed computations |
| 503 | -- | 509 | R. D. Hersch, F. Maddaleno, C. Nicks, M. Bürki. The video-ram multiprocessor architecture |
| 511 | -- | 518 | Valmir C. Barbosa, Felipe M. G. França. Specification of a communication virtual processor for parallel processing systems |
| 519 | -- | 524 | Gerard J. M. Smit, Pierre G. Jansen. The communication processor of TUMULT-64 |
| 527 | -- | 534 | R. Rauscher, P. Kückendahl, M. Payer. A system for estimation of numerical stability for matrix operations in systolic arrays |
| 535 | -- | 539 | N. Stanley Scott, Lionel C. Waring, Peter Milligan, Danny Crookes, P. L. Kilpatrick, Philip J. Morrow. A comparison of programming paradigms for the parallel computation of racah coefficients: An application of transputers to computational atomic physics |
| 541 | -- | 546 | Thomas Bemmerl, Thomas Bonk. Optimizing cache parameters using CAE workstations |
| 549 | -- | 553 | A. T. Clarke, B. M. Brown, M. P. Thorne. Using a micro to automate data acquisition in music publishing |
| 555 | -- | 561 | Peter J. Comerford, Barry Eaglestone. Bradford musical instrument simulator and workstation |
| 563 | -- | 0 | Daniel Tabak. Microelectronics: Processor architectures I |
| 565 | -- | 572 | Antonio González 0001, José María Llabería, Jordi Cortadella. A mechanism for reducing the cost of branches in RISC architectures |
| 573 | -- | 580 | Jordi Cortadella, Teodor Jové. Designing a branch target buffer for executing branches with zero time cost in a RISC processor |
| 581 | -- | 588 | Manuel Lois Anido, David J. Allerton, E. J. Zaluska. The architecture of RIG: A RISC for image generation in a multi-microprocessor environment |
| 589 | -- | 596 | A. Dumont, E. Gilson, C. Trullemans. BRISC: A RISC biprocessor architecture dedicated to power applications |
| 597 | -- | 0 | Rüdiger W. Brause. Parallel processing: Function-directed and neural architectures |
| 599 | -- | 606 | Rubén González-Rubio, Michel Couprie. DDC: Delta driven computer, and μSyC: microprogrammable symbolic coprocessor |
| 607 | -- | 611 | M. De Blasi, A. Gentile, G. Lopez, A. Franco. Parallel backtracking prolog engine |
| 613 | -- | 620 | Nathalie Devesa, Gilles Goncalves, Marie-Paule Lecouffe, Bernard Toursel. A controlled reduction model of functional programs on a distributed associative network |
| 621 | -- | 626 | Jeremy Cook, John Gilbert. Parallel neural network simulation using sparse matrix techniques |
| 627 | -- | 0 | Fausto Distante. Parallel processing: Array processors I |
| 629 | -- | 636 | Vincenzo Piuri. Fault-tolerant hexagonal arithmetic array processors |
| 637 | -- | 645 | Luca Breveglieri. Design and implementation of a VLSI serial multiplier for fixed point numbers with self-checking capability |
| 647 | -- | 654 | Emilio L. Zapata, Ramon Doallo, Francisco F. Rivera, M. A. Ismail. A VLSI systolic architecture for fuzzy clustering |
| 655 | -- | 660 | S. F. Reddaway, Roderic M. R. Page. High speed data searching with a processor array |
| 661 | -- | 0 | Jukka Karjalainen. Applications: Real time systems |
| 663 | -- | 672 | Hans Kurmann, Bogdan Lent, Reto Marti. Declarative programming of the embedded control systems based on OR-ed dataflow operational principle |
| 673 | -- | 680 | A. Katbab. A multiprocessor architecture for robot-arm control |
| 681 | -- | 686 | Miroslav Jockovic. An application of petri-nets in the control system of the FTC |
| 687 | -- | 692 | Wolfgang A. Halang. Parallel administration of events in real-time systems |
| 693 | -- | 0 | Daniel Tabak. Microelectronics: Processor architectures II |
| 695 | -- | 700 | Vojin G. Oklobdzija. Issues in CPU-coprocessor communication and synchronization |
| 701 | -- | 707 | Eddy H. Debaere. A language coprocessor as a HLL directed architecture |
| 709 | -- | 713 | Elliot J. Cohen, Reuven A. Marko, Jonathan Levy. Integrating an on-chip MMU into a highly pipelined architecture |
| 715 | -- | 0 | Mario Dal Cin. Session G2: Parallel processing: Fault tolerance I |
| 717 | -- | 721 | Nick Kanopoulos, Peter N. Marinos. Design of a bus-monitor for real-time applications |
| 723 | -- | 730 | Kaiyuan Huang. Diagnosability of system faults with propagation under asymmetric invalidation |
| 731 | -- | 734 | Jerzy Tyszer. Multiple fault diagnosis for interconnection networks for distributed systems |
| 737 | -- | 742 | Massimo Maresca, Hungwen Li. A VLSI implementation of polymorphic-torus architecture |
| 743 | -- | 746 | Shi-yao Jin, Shuan Zhao, Shi-Sheng Yie. A vectorized superminicomputer, VAX-11/700 with vector processing |
| 747 | -- | 754 | Argy Krikelis, R. Mike Lea. An associative string processor architecture for parallel processing applications |
| 755 | -- | 0 | Friedrich Winkelhage. Applications: Education I |
| 757 | -- | 760 | Alan Chalmers. OCCAM - The language for educating future parallel programmers? |
| 761 | -- | 765 | Michael Collier. A software training environment for electronic engineers using unix, modula-2 and a local area network |
| 767 | -- | 772 | Paul Loewenstein, Andrew Fox. Closing the semantic gap |
| 773 | -- | 0 | Roberto Negrini. Microelectronics: Fault tolerance and reliability |
| 775 | -- | 782 | G. A. S. Wingate, C. Preece. Transient fault recovery assessment in 8 and 16 bit microprocessor based controllers in embedded systems |
| 783 | -- | 789 | Janusz Sosnowski. Concurrent checking of program flow using single-chip microcomputers |
| 791 | -- | 0 | Mario Dal Cin. Parallel processing: Fault Tolerance II |
| 793 | -- | 799 | Geoffrey F. Carpenter. State space modelling in the design of robust software for distributed systems: A case study |
| 801 | -- | 806 | D. J. Holding, M. R. Hill, G. F. Carpenter. The design of distributed, software fault tolerant, real-time systems incorporating decision mechanisms |
| 807 | -- | 0 | Rüdiger W. Brause. Session H3: Parallel processing: Concurrent program design |
| 809 | -- | 818 | Antti Valmari. PC-Rimst - a tool for validating concurrent program designs |
| 819 | -- | 826 | Peter Brezany. Parallel parsing in a multiprocessor environment |
| 827 | -- | 0 | Friedrich Winkelhage. Session H4: Applications: Education II |
| 829 | -- | 833 | Ulf Sandberg, Torsten Cegrell. Computer systems for real-time process control and supervision A framework for education based on a systems-engineering approach |
| 835 | -- | 840 | Richard N. Zobel. Real-time systems education in computer science at Manchester University |