| 3 | -- | 5 | Partha Kundu, Li-Shiuan Peh. Guest Editors Introduction: On-Chip Interconnects for Multicores |
| 6 | -- | 14 | Thomas William Ainsworth, Timothy Mark Pinkston. Characterizing the Cell EIB On-Chip Network |
| 15 | -- | 31 | David Wentzlaff, Patrick Griffin, Henry Hoffmann, Liewei Bao, Bruce Edwards, Carl Ramey, Matthew Mattina, Chyi-Chang Miao, John F. Brown III, Anant Agarwal. On-Chip Interconnection Architecture of the Tile Processor |
| 32 | -- | 40 | Mike Butts. Synchronization through Communication in a Massively Parallel Processor Array |
| 41 | -- | 50 | Paul Gratz, Changkyu Kim, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger. On-Chip Interconnection Networks of the TRIPS Chip |
| 51 | -- | 61 | Yatin Hoskote, Sriram Vangal, Arvind Singh, Nitin Borkar, Shekhar Borkar. A 5-GHz Mesh Interconnect for a Teraflops Processor |
| 62 | -- | 74 | David Arditti Ilitzky, Jeffrey D. Hoffman, Anthony Chun, Brando Perez Esparza. Architecture of the Scalable Communications Core s Network on Chip |
| 75 | -- | 85 | Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini. Bringing NoCs to 65 nm |
| 86 | -- | 95 | Ümit Y. Ogras, Radu Marculescu, Hyung Gyu Lee, Puru Choudhary, Diana Marculescu, Michael Kaufman, Peter Nelson. Challenges and Promising Results in NoC Prototyping Using FPGAs |
| 96 | -- | 108 | John D. Owens, William J. Dally, Ron Ho, D. N. Jayasimha, Stephen W. Keckler, Li-Shiuan Peh. Research Challenges for On-Chip Interconnection Networks |
| 109 | -- | 110 | Richard Stern. Federal Appeals Court Sees Potential Antitrust Violation in Standardization Skullduggery |
| 111 | -- | 112 | Shane Greenstein. Dog Days for Broadband |