External Links

    Journal: IEEE Micro

    Volume 27, Issue 6

    6 -- 0David H. Albonesi. Productive and Healthy Debate
    8 -- 10Shane Greenstein. Innovation at the Edges
    11 -- 13Richard Stern. Supreme Court to Hear Semiconductor Chip Patent Exhaustion Case
    14 -- 24Joel S. Emer, Mark D. Hill, Yale N. Patt, Joshua J. Yi, Derek Chiou, Resit Sendag. Single-Threaded vs. Multithreaded: Where Should We Focus?
    25 -- 35Shay Gueron, Jean-Pierre Seifert, Geoffrey Strongin, Derek Chiou, Resit Sendag, Joshua J. Yi. Where Does Security Stand? New Vulnerabilities vs. Trusted Computing
    36 -- 45Antonio González, Scott A. Mahlke, Shubu Mukherjee, Resit Sendag, Derek Chiou, Joshua J. Yi. Reliability: Fallacy or Reality?
    46 -- 57Kevin Skadron, Pradip Bose, Kanad Ghose, Resit Sendag, Joshua J. Yi, Derek Chiou. Low-Power Design and Temperature Management
    60 -- 61Richard Mateosian. Advice for Investigators
    62 -- 64Philip G. Emma. You re Invited to a Party! (How To Hold a Collaborative IP-Development Session)

    Volume 27, Issue 5

    3 -- 5Partha Kundu, Li-Shiuan Peh. Guest Editors Introduction: On-Chip Interconnects for Multicores
    6 -- 14Thomas William Ainsworth, Timothy Mark Pinkston. Characterizing the Cell EIB On-Chip Network
    15 -- 31David Wentzlaff, Patrick Griffin, Henry Hoffmann, Liewei Bao, Bruce Edwards, Carl Ramey, Matthew Mattina, Chyi-Chang Miao, John F. Brown III, Anant Agarwal. On-Chip Interconnection Architecture of the Tile Processor
    32 -- 40Mike Butts. Synchronization through Communication in a Massively Parallel Processor Array
    41 -- 50Paul Gratz, Changkyu Kim, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger. On-Chip Interconnection Networks of the TRIPS Chip
    51 -- 61Yatin Hoskote, Sriram Vangal, Arvind Singh, Nitin Borkar, Shekhar Borkar. A 5-GHz Mesh Interconnect for a Teraflops Processor
    62 -- 74David Arditti Ilitzky, Jeffrey D. Hoffman, Anthony Chun, Brando Perez Esparza. Architecture of the Scalable Communications Core s Network on Chip
    75 -- 85Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini. Bringing NoCs to 65 nm
    86 -- 95Ümit Y. Ogras, Radu Marculescu, Hyung Gyu Lee, Puru Choudhary, Diana Marculescu, Michael Kaufman, Peter Nelson. Challenges and Promising Results in NoC Prototyping Using FPGAs
    96 -- 108John D. Owens, William J. Dally, Ron Ho, D. N. Jayasimha, Stephen W. Keckler, Li-Shiuan Peh. Research Challenges for On-Chip Interconnection Networks
    109 -- 110Richard Stern. Federal Appeals Court Sees Potential Antitrust Violation in Standardization Skullduggery
    111 -- 112Shane Greenstein. Dog Days for Broadband

    Volume 27, Issue 4

    0 -- 0Shane Greenstein. The 15-Billion-Dollar Broadband Bonus
    3 -- 4David H. Albonesi. Mixing It Up
    6 -- 20Assaf Shacham, Keren Bergman. Building Ultralow-Latency Interconnection Networks Using Photonic Integration
    21 -- 33Li Zhao, Ravi R. Iyer, Jaideep Moses, Ramesh Illikkal, Srihari Makineni, Donald Newell. Exploring Large-Scale CMP Architectures Using ManySim
    34 -- 48Jianwei Chen, Michel Dubois, Per Stenström. SimWattch: Integrating Complete-System and User-Level Performance and Power Simulators
    49 -- 57Ivan Gonzalez, Estanislao Aguayo, Sergio López-Buedo. Self-Reconfigurable Embedded Systems on Low-Cost FPGAs
    59 -- 61Richard Mateosian. Thinking about Technology
    62 -- 64Philip G. Emma. Innovation or Notoriety?

    Volume 27, Issue 3

    4 -- 5David H. Albonesi. More Hot Stuff
    6 -- 7Shane Greenstein. Did the Price of the Internet Drop?
    8 -- 29Tim Harris, Adrián Cristal, Osman S. Unsal, Eduard Ayguadé, Fabrizio Gagliardi, Burton Smith, Mateo Valero. Transactional Memory: An Overview
    31 -- 48Gabriel H. Loh, Yuan Xie, Bryan Black. Processor Design in 3D Die-Stacking Technologies
    49 -- 62David Brooks, Robert P. Dick, Russ Joseph, Li Shang. Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors
    63 -- 72Kenneth Hoste, Lieven Eeckhout. Microarchitecture-Independent Workload Characterization
    74 -- 93Benjamin C. Lee, David M. Brooks. Spatial Sampling and Regression Strategies
    94 -- 105Serag GadelRab. 10-Gigabit Ethernet Connectivity for Computer Servers
    106 -- 109Richard Stern. Antitrust Division Gives IEEE Standard Setters the Okay to Ask Patentees How RAND They Are
    110 -- 112Philip G. Emma. Arcane Facts and New Words: Expanding Your Creative Talent

    Volume 27, Issue 2

    0 -- 0Shane Greenstein. Wagging Wikipedia s long tail
    4 -- 5David H. Albonesi. Editor in Chief s Message: Truly hot chips - Do we still care?
    7 -- 9John Kubiatowicz, Howard Sachs. Guest Editors Introduction: Hot Chips 18
    10 -- 21Pat Conway, Bill Hughes. The AMD Opteron Northbridge Architecture
    22 -- 33Sivakumar Radhakrishnan, Sundaram Chinthamani, Kai Cheng. The Blackford Northbridge Chipset for the Intel 5000
    34 -- 45Bevan M. Baas, Zhiyi Yu, Michael J. Meeuwsen, Omar Sattari, Ryan W. Apperson, Eric W. Work, Jeremy W. Webb, Michael A. Lai, Tinoosh Mohsenin, Dean Truong, Jason Cheung. AsAP: A Fine-Grained Many-Core Platform for DSP Applications
    46 -- 57John Wawrzynek, David A. Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic. RAMP: Research Accelerator for Multiple Processors
    58 -- 68Arjan Bink, Richard York. ARM996HS: The First Licensable, Clockless 32-Bit Processor Core
    69 -- 78Tse-Yu Yeh. Low-Power, High-Performance Architecture of the PWRficient Processor Family
    80 -- 82Richard Stern. Coming down the home stretch in the Rambus standardization skullduggery saga: To levy or not to levy royalties
    83 -- 85Richard Mateosian. Looking Back
    86 -- 88Philip G. Emma. Supercharging Your Creative Skills

    Volume 27, Issue 1

    0 -- 133Shane Greenstein. The High Cost of a Cheap Lesson
    5 -- 6David H. Albonesi. Standing on Solid Ground
    8 -- 11Ronny Ronen, Antonio González. Guest Editors Introduction: Micro s Top Picks from the Microarchitecture Conferences
    12 -- 25Smruti R. Sarangi, Satish Narayanasamy, Bruce Carneal, Abhishek Tiwari, Brad Calder, Josep Torrellas. Patching Processor Design Errors with Programmable Hardware
    26 -- 35Shan Lu, Joseph Tucek, Feng Qin, Yuanyuan Zhou. AVIO: Detecting Atomicity Violations via Access-Interleaving Invariants
    36 -- 47George A. Reis, Jonathan Chang, David I. August. Automatic Instruction-Level Software-Only Recovery
    48 -- 55Min Xu, Rastislav Bodík, Mark D. Hill. A Hardware Memory Race Recorder for Deterministic Replay
    56 -- 66Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi. On-Chip Optical Technology in Future Bus-Based Multicore Designs
    67 -- 76Austen McDonald, Brian D. Carlstrom, JaeWoong Chung, Chi Cao Minh, Hassan Chafi, Christos Kozyrakis, Kunle Olukotun. Transactional Memory: The Hardware-Software Interface
    77 -- 83Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood. 3D Integration for Introspection
    84 -- 93Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith. A Top-Down Approach to Architecting CPI Component Performance Counters
    94 -- 104Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt. Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication
    106 -- 113Tingting Sha, Milo M. K. Martin, Amir Roth. NoSQ: Store-Load Communication without a Store Queue
    114 -- 123Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner. SODA: A High-Performance DSP Architecture for Software-Defined Radio
    124 -- 126Richard Stern. West Coast Federal Appeals Court Upholds Chip Protection Act Violation Finding
    128 -- 130Richard Mateosian. Economics
    134 -- 136Philip G. Emma. Reinventing Entrepreneurial Inventing for the 21st Century
    runs on