| 5 | -- | 0 | Pradip Bose. Computer architecture research: Shifting priorities and newer challenges |
| 6 | -- | 0 | Shane Greenstein. Canaries, whips, and sails |
| 8 | -- | 9 | David H. Albonesi. Guest Editor s Introduction: Micro s Top Picks from Microarchitecture Conferences |
| 10 | -- | 20 | Dan Ernst, Shidhartha Das, Seokwoo Lee, David Blaauw, Todd M. Austin, Trevor N. Mudge, Nam Sung Kim, Krisztián Flautner. Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation |
| 22 | -- | 29 | Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas Nowatzyk. Fingerprinting: Bounding Soft-Error-Detection Latency and Bandwidth |
| 30 | -- | 37 | Christopher T. Weaver, Joel S. Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt. Reducing the Soft-Error Rate of a High-Performance Microprocessor |
| 38 | -- | 49 | Xiaodong Li, Zhenmin Li, Pin Zhou, Yuanyuan Zhou, Sarita V. Adve, Sanjeev Kumar. Performance-Directed Energy Management for Storage Systems |
| 50 | -- | 56 | Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou, Josep Torrellas. iWatcher: Simple, General Architectural Support for Software Debugging |
| 57 | -- | 61 | Brian A. Fields, Rastislav Bodík, Mark D. Hill, Chris J. Newburn. Interaction Cost: For When Event Counts Just Don t Add Up |
| 62 | -- | 73 | Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkary, Amit Gandhi, Michael Upton. Continual Flow Pipelines: Achieving Resource-Efficient Latency Tolerance |
| 74 | -- | 82 | Perry H. Wang, Jamison D. Collins, Hong Wang 0003, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen. Helper Threads via Virtual Multithreading |
| 84 | -- | 90 | Ronny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian Pharris, Jared Casper, Krste Asanovic. The Vector-Thread Architecture |
| 92 | -- | 103 | Lance Hammond, Brian D. Carlstrom, Vicky Wong, Michael K. Chen, Christos Kozyrakis, Kunle Olukotun. Transactional Coherence and Consistency: Simplifying Parallel Hardware and Software |
| 104 | -- | 109 | Jaehyuk Huh, Doug Burger, Jichuan Chang, Gurindar S. Sohi. Speculative Incoherent Cache Protocols |
| 110 | -- | 117 | Harold W. Cain, Mikko H. Lipasti. Memory Ordering: A Value-Based Approach |
| 118 | -- | 127 | Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler. Scalable Hardware Memory Disambiguation for High-ILP Processors |
| 133 | -- | 134 | Richard Mateosian. Micro Review: More on old themes |