Journal: IEEE Micro

Volume 33, Issue 6

2 -- 0Erik R. Altman. Cool Chips, Mobile Devices, Memory, and IEEE Micro Going Digital
4 -- 5Makoto Ikeda, Fumio Arakawa. Cool Chips
6 -- 15Noriyuki Miura, Yusuke Koizumi, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura. A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface
16 -- 24Toshio Yoshida, Takumi Maruyama, Yasunobu Akizuki, Ryuji Kan, Naohiro Kiyota, Kiyoshi Ikenishi, Shigeki Itou, Tomoyuki Watahiki, Hiroshi Okano. Sparc64 X: Fujitsu's New-Generation 16-Core Processor for Unix Servers
26 -- 36Kazuki Fukuoka, Noriaki Maeda, Koji Nii, Masaki Fujigaya, Noriaki Sakamoto, Takao Koike, Takahiro Irita, Kohei Wakahara, Tsugio Matsuyama, Keiji Hasegawa, Toshiharu Saito, Akira Fukuda, Kaname Teranishi, Takeshi Kataoka, Toshihiro Hattori. Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor
38 -- 46Rumi Zahir, Mark Ewert, Hari Seshadri. The Medfield Smartphone: Intel Architecture in a Handheld Form Factor
47 -- 55Todor Cooklev, Akinori Nishihara. An Open RF-Digital Interface for Software-Defined Radios
56 -- 65Bendik Kleveland, Michael John Miller, Ronald B. David, Jay Patel, Rajesh Chopra, Dipak K. Sikdar, Jeff Kumala, Socrates D. Vamvakos, Mike Morrison, Ming Liu, Jayaprakash Balachandran. An Intelligent RAM with Serial I/Os
66 -- 74Jing Guo, Liyi Xiao, Zhigang Mao, Qiang Zhao. Novel Mixed Codes for Multiple-Cell Upsets Mitigation in Static RAMs
76 -- 78Richard Mateosian. Technical Design
80 -- 0Shane Greenstein. How Much Apache?

Volume 33, Issue 5

4 -- 5Erik R. Altman. Dark Silicon and Dangerous Predictions
6 -- 7Michael Bedford Taylor, Steven Swanson. Dark Silicon [Guest editors' introduction]
8 -- 19Michael B. Taylor. A Landscape of the New Dark Silicon Design Regime
20 -- 28Arun Raghavan, Laurel Emurian, Lei Shao, Marios C. Papaefthymiou, Kevin P. Pipe, Thomas F. Wenisch, Milo M. K. Martin. Utilizing Dark Silicon to Save Energy with Computational Sprinting
30 -- 37Nathaniel Ross Pinckney, Ronald G. Dreslinski, Korey Sewell, David Fick, Trevor N. Mudge, Dennis Sylvester, David Blaauw. Limits of Parallelism and Boosting in Dim Silicon
40 -- 48Liang Wang, Kevin Skadron. Implications of the Power Wall: Dim Cores and Reconfigurable Logic
50 -- 59Karthik Swaminathan, Emre Kultursay, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Suman Datta. Steep-Slope Devices: From Dark to Dim Silicon
60 -- 61Rich Belgard. Joseph A. (Josh) Fisher Receives the 2012 IEEE B. Ramakrishna Rau Award
62 -- 63Shane Greenstein. Digital Public Goods

Volume 33, Issue 4

2 -- 0Erik R. Altman. Reliability, Theme Issues, and Plagiarism
4 -- 5Vijay Janapa Reddi. Reliability-Aware Microarchitecture Design
6 -- 14Ulya R. Karpuzcu, Nam Sung Kim, Josep Torrellas. Coping with Parametric Variation at Near-Threshold Voltages
16 -- 24Hao Wang, Nam Sung Kim. Improving Throughput of Power-Constrained Many-Core Processors Based on Unreliable Devices
26 -- 34David J. Palframan, Nam Sung Kim, Mikko H. Lipasti. Resilient High-Performance Processors with Spare RIBs
35 -- 45Charles Lefurgy, Alan J. Drake, Michael S. Floyd, Malcolm Allen-Ware, Bishop Brock, José A. Tierno, John B. Carter, Robert W. Berry. Active Guardband Management in Power7+ to Save Energy and Maintain Reliability
46 -- 55Veit Kleeberger, Christina Gimmler-Dumont, Christian Weis, Andreas Herkersdorf, Daniel Mueller-Gritschneder, Sani R. Nassif, Ulf Schlichtmann, Norbert Wehn. A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience
56 -- 65Lukasz G. Szafaryn, Brett H. Meyer, Kevin Skadron. Evaluating Overheads of Multibit Soft-Error Protection in the Processor Core
66 -- 75Youngtaek Kim, Lizy Kurian John, Sanjay Pant, Srilatha Manne, Michael J. Schulte, William Lloyd Bircher, Madhu Saravana Sibi Govindan. Automating Stressmark Generation for Testing Processor Voltage Fluctuations
78 -- 79Shane Greenstein. Platform Conflicts

Volume 33, Issue 3

2 -- 0Erik R. Altman. Ten Years of Top Picks
4 -- 7Babak Falsafi, Gabriel H. Loh. Top Picks from the 2012 Computer Architecture Conferences
8 -- 15Arun Raghavan, Yixin Luo, Anuj Chandawalla, Marios C. Papaefthymiou, Kevin P. Pipe, Thomas F. Wenisch, Milo M. K. Martin. Designing for Responsiveness with Computational Sprinting
16 -- 27Hadi Esmaeilzadeh, Adrian Sampson, Luis Ceze, Doug Burger. Neural Acceleration for General-Purpose Approximate Programs
28 -- 37Daniel Wong 0001, Murali Annavaram. Scaling the Energy Proportionality Wall with KnightShift
38 -- 47Santosh Nagarakatte, Milo M. K. Martin, Steve Zdancewic. Hardware-Enforced Comprehensive Memory Safety
48 -- 56Jonathan Kaveh Valamehr, Melissa Chase, Seny Kamara, Andrew Putnam, Daniel Shumow, Vinod Vaikuntanathan, Timothy Sherwood. Inspection-Resistant Memory Architectures
58 -- 66Siva Kumar Sastry Hari, Sarita V. Adve, Helia Naeimi, Pradeep Ramachandran. Relyzer: Application Resiliency Analyzer for Transient Faults
68 -- 77John Demme, Robert Martin, Adam Waksman, Simha Sethumadhavan. A Quantitative, Experimental Approach to Measuring Processor Side-Channel Security
78 -- 85Timothy G. Rogers, Mike O'Connor, Tor M. Aamodt. Cache-Conscious Thread Scheduling for Massively Multithreaded Processors
86 -- 94Melanie Kambadur, Kui Tang, Martha A. Kim. Parallel Block Vectors: Collection, Analysis, and Uses
96 -- 104Abhayendra Singh, Satish Narayanasamy, Daniel Marino, Todd D. Millstein, Madanlal Musuvathi. A Safety-First Approach to Memory Models
106 -- 115Mahdi Nazm Bojnordi, Engin Ipek. Programmable DDRx Controllers
116 -- 118Richard Mateosian. Unconscious Meaning
120 -- 0Shane Greenstein. Differentiated Platforms

Volume 33, Issue 2

4 -- 5Erik R. Altman. Hot Chips and the Incomplete Job of Exploiting Them
6 -- 7Christos Kozyrakis, Rumi Zahir. Selected Research from Hot Chips 24
8 -- 16Ronald G. Dreslinski, David Fick, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Dennis Sylvester, David Blaauw, Trevor N. Mudge. Centip3De: A 64-Core, 3D Stacked Near-Threshold System
18 -- 26Robert Rogenmoser, Lawrence T. Clark. Reducing Transistor Variability for High Performance Low Power Chips
28 -- 36Gregory Ruhl, Saurabh Dighe, Shailendra Jain, Surhud Khare, Sriram R. Vangal. IA-32 Processor with a Wide-Voltage-Operating Range in 32-nm CMOS
38 -- 47C. Kevin Shum, Fadi Busaba, Christian Jacobi. IBM zEC12: The Third-Generation High-Frequency Mainframe Microprocessor
48 -- 57John R. Feehrer, Sumti Jairath, Paul Loewenstein, Ram Sivaramakrishnan, David Smentek, Sebastian Turullols, Ali Vahidsafa. The Oracle Sparc T5 16-Core Processor Scales to Eight Sockets
60 -- 61Richard Mateosian. Ethics of Big Data
62 -- 63Shane Greenstein. The Online Honesty Box