| 1 | -- | 2 | Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete. Guests editor s introduction |
| 3 | -- | 9 | Hanene Ben Fradj, Asmaa el Ouardighi, Cécile Belleudy, Michel Auguin. Energy aware memory architecture configuration |
| 10 | -- | 16 | Hyo-Joong Suh, Sung Woo Chung. DRACO: optimized CC-NUMA system with novel dual-link interconnections to reduce the memory latency |
| 17 | -- | 24 | Sami Yehia, Jean-Francois Collard, Olivier Temam. Load squared: adding logic close to memory to reduce the latency of indirect loads with high miss ratios |
| 25 | -- | 32 | Hiroaki Kobayashi, Isao Kotera, Hiroyuki Takizawa. Locality analysis to control dynamically way-adaptable caches |
| 33 | -- | 40 | Fumio Arakawa, Makoto Ishikawa, Yuki Kondo, Tatsuya Kamei, Motokazu Ozawa, Osamu Nishii, Toshihiro Hattori. SH-X: an embedded processor core for consumer appliances |
| 41 | -- | 48 | Afrin Naz, Mehran Rezaei, Krishna M. Kavi, Philip H. Sweany. Improving data cache performance with integrated use of split caches, victim cache and stream buffers |
| 49 | -- | 56 | Alex Pajuelo, Antonio González, Mateo Valero. Speculative execution for hiding memory latency |
| 57 | -- | 62 | Javier Verdú, Jorge García, Mario Nemirovsky, Mateo Valero. The impact of traffic aggregation on the memory performance of networking applications |
| 63 | -- | 71 | Bramha Allu, Wei Zhang 0002. Exploiting the replication cache to improve performance for multiple-issue microprocessors |
| 72 | -- | 74 | Mark Thorson. Internet nuggets |