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    Journal: SIGARCH Computer Architecture News

    Volume 33, Issue 5

    1 -- 2David R. Kaeli, Robert Cohn. Introduction to the special issue
    3 -- 8Chunling Hu, John McCabe, Daniel A. Jiménez, Ulrich Kremer. The Camino Compiler infrastructure
    9 -- 14Martin Schulz, Dong H. Ahn, Andrew Bernat, Bronis R. de Supinski, Steven Y. Ko, Gregory L. Lee, Barry Rountree. Scalable dynamic binary instrumentation for Blue Gene/L
    15 -- 20Edson Borin, Cheng Wang, Youfeng Wu, Guido Araujo. Dynamic binary control-flow errors detection
    21 -- 26Micha Moffie, David R. Kaeli. ASM: application security monitor
    27 -- 32Qin Zhao, Rodric M. Rabbah, Weng-Fai Wong. Dynamic memory optimization using pool allocation and prefetching
    33 -- 38Xiaofeng Gao, Beth Simon, Allan Snavely. ALITER: an asynchronous lightweight instrumentation tool for event recording
    39 -- 44Collin McCurdy, Charles N. Fischer. Using Pin as a memory reference generator for multiprocessor simulation
    45 -- 50Heidi Pan, Krste Asanovic, Robert Cohn, Chi-Keung Luk. Controlling program execution through binary instrumentation
    51 -- 56Nikrouz Faroughi. Profiling of parallel processing programs on shared memory multiprocessors using Simics
    57 -- 62Naveen Kumar, Ramesh Peri. Transparent debugging of dynamically instrumented programs
    63 -- 68Laune C. Harris, Barton P. Miller. Practical analysis of stripped binary code
    69 -- 74Vijay Janapa Reddi, Dan Connors, Robert S. Cohn. Persistence in dynamic code transformation systems
    75 -- 80Ram Srinivasan, Olaf M. Lubeck. MonteSim: a Monte Carlo performance model for in-order microachitectures
    81 -- 86Michael Laurenzano, Beth Simon, Allan Snavely, Meghan Gunn. Low cost trace-driven memory simulation using SimPoint
    87 -- 93Mark Thorson. Internet nuggets

    Volume 33, Issue 4

    4 -- 0Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen. Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP 05)
    5 -- 13James Laudon. Performance/Watt: the new server focus
    14 -- 23John D. Davis, Cong Fu, James Laudon. The RASE (Rapid, Accurate Simulation Environment) for chip multiprocessors
    24 -- 33Lisa R. Hsu, Ravishankar R. Iyer, Srihari Makineni, Steven K. Reinhardt, Donald Newell. Exploring the cache design space for large scale CMPs
    34 -- 43John D. Davis, Stephen E. Richardson, Charis Charitsis, Kunle Olukotun. A chip prototyping substrate: the flexible architecture for simulation and testing (FAST)
    44 -- 53Neil Vachharajani, Matthew Iyer, Chinmay Ashok, Manish Vachharajani, David I. August, Daniel A. Connors. Chip multi-processor scalability for single-threaded applications
    54 -- 63Julia Chen, Philo Juang, Kevin Ko, Gilberto Contreras, David Penry, Ram Rangan, Adam Stoler, Li-Shiuan Peh, Margaret Martonosi. Hardware-modulated parallelism in chip multiprocessors
    64 -- 69Jack Sampson, Ruben Gonzalez, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker. Fast synchronization for chip multiprocessors
    70 -- 79Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi, Suleyman Sair, Timothy Sherwood. Dynamically configurable shared CMP helper engines for improved performance
    80 -- 91Theofanis Constantinou, Yiannakis Sazeides, Pierre Michaud, Damien Fetis, André Seznec. Performance implications of single thread migration on a chip multi-core
    92 -- 99Milo M. K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, David A. Wood. Multifacet s general execution-driven multiprocessor simulator (GEMS) toolset
    100 -- 107David Wang, Brinda Ganesh, Nuengwong Tuaycharoen, Kathleen Baynes, Aamer Jaleel, Bruce L. Jacob. DRAMsim: a memory system simulator
    108 -- 112Barry Rountree, Robert Springer, David K. Lowenthal, Vincent W. Freeh. Notes from HPPAC 2005
    113 -- 120H. C. Wang, C. K. Yuen. A general framework to build new CPUs by mapping abstract machine code to instruction level parallel execution hardware
    121 -- 127Nana B. Sam, Martin Burtscher. Improving memory system performance with energy-efficient value speculation
    128 -- 133Mark Thorson. Internet Nuggets

    Volume 33, Issue 3

    1 -- 2Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete. Guests editor s introduction
    3 -- 9Hanene Ben Fradj, Asmaa el Ouardighi, Cécile Belleudy, Michel Auguin. Energy aware memory architecture configuration
    10 -- 16Hyo-Joong Suh, Sung Woo Chung. DRACO: optimized CC-NUMA system with novel dual-link interconnections to reduce the memory latency
    17 -- 24Sami Yehia, Jean-Francois Collard, Olivier Temam. Load squared: adding logic close to memory to reduce the latency of indirect loads with high miss ratios
    25 -- 32Hiroaki Kobayashi, Isao Kotera, Hiroyuki Takizawa. Locality analysis to control dynamically way-adaptable caches
    33 -- 40Fumio Arakawa, Makoto Ishikawa, Yuki Kondo, Tatsuya Kamei, Motokazu Ozawa, Osamu Nishii, Toshihiro Hattori. SH-X: an embedded processor core for consumer appliances
    41 -- 48Afrin Naz, Mehran Rezaei, Krishna M. Kavi, Philip H. Sweany. Improving data cache performance with integrated use of split caches, victim cache and stream buffers
    49 -- 56Alex Pajuelo, Antonio González, Mateo Valero. Speculative execution for hiding memory latency
    57 -- 62Javier Verdú, Jorge García, Mario Nemirovsky, Mateo Valero. The impact of traffic aggregation on the memory performance of networking applications
    63 -- 71Bramha Allu, Wei Zhang 0002. Exploiting the replication cache to improve performance for multiple-issue microprocessors
    72 -- 74Mark Thorson. Internet nuggets

    Volume 33, Issue 1

    2 -- 5David M. Chess. Security in autonomic computing
    6 -- 15Weidong Shi, Hsien-Hsin S. Lee, Chenghuai Lu, Mrinmoy Ghosh. Towards the issues in architectural support for protection of software execution
    16 -- 26John Patrick McGregor, Ruby B. Lee. Protecting cryptographic keys and computations via virtual secure coprocessing
    27 -- 33Brian Rogers, Yan Solihin, Milos Prvulovic. Memory predecryption: hiding the latency overhead of memory encryption
    34 -- 41David A. Holland, Ada T. Lim, Margo I. Seltzer. An architecture a day keeps the hacker away
    42 -- 47Stelios Sidiroglou, Michael E. Locasto, Angelos D. Keromytis. Hardware support for self-healing software services
    48 -- 57Jedidiah R. Crandall, Frederic T. Chong. A security assessment of the minos architecture
    58 -- 64Matthew Burnside, Angelos D. Keromytis. The case for crypto protocol awareness inside the OS kernel
    65 -- 72Marc L. Corliss, E. Christopher Lewis, Amir Roth. Using DISE to protect return addresses from attack
    73 -- 80Dong Ye, David R. Kaeli. A reliable return address stack: microarchitectural features to defeat stack smashing
    81 -- 89Koji Inoue. Energy-security tradeoff in a secure cache architecture against buffer overflow attacks
    90 -- 98Derek Uluski, Micha Moffie, David R. Kaeli. Characterizing antivirus workload execution
    99 -- 107Monther Aldwairi, Thomas M. Conte, Paul D. Franzon. Configurable string matching hardware for speeding up intrusion detection
    108 -- 117Milena Milenkovic, Aleksandar Milenkovic, Emil Jovanov. Using instruction block signatures to counter code injection attacks
    118 -- 123Youtao Zhang, Jun Yang, Yongjing Lin, Lan Gao. Architectural support for protecting user privacy on trusted processors
    124 -- 133Masaaki Shirase, Yasushi Hibino. An architecture for elliptic curve cryptograph computation
    134 -- 143Taeho Kgil, Laura Falk, Trevor N. Mudge. ChipLock: support for secure microarchitectures
    144 -- 147Magnus Ekman, Fredrik Warg, Jim Nilsson. An in-depth look at computer performance growth
    148 -- 155N. Venkateswaran, S. Balaji, V. Sridhar. Fault tolerant bus architecture for deep submicron based processors
    156 -- 160Mark Thorson. Internet nuggets
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