Journal: TACO

Volume 1, Issue 4

369 -- 388Allan Hartstein, Thomas R. Puzak. The optimum pipeline depth considering both power and performance
389 -- 417Adrián Cristal, Oliverio J. Santana, Mateo Valero, José F. Martínez. Toward kilo-instruction processors
418 -- 444Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan. An analysis of a resource efficient checkpoint architecture
445 -- 475Chia-Lin Yang, Alvin R. Lebeck, Hung-Wei Tseng, Chien-Hao Lee. Tolerating memory latency through push prefetching for pointer-intensive applications

Volume 1, Issue 3

247 -- 271Jin Lin, Tong Chen, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai, Sun Chan. A compiler framework for speculative optimizations
272 -- 304Brian A. Fields, Rastislav Bodík, Mark D. Hill, Chris J. Newburn. Interaction cost and shotgun profiling
305 -- 322Karthik Sankaranarayanan, Kevin Skadron. Profile-based adaptation for cache decay
323 -- 367Fen Xie, Margaret Martonosi, Sharad Malik. Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling

Volume 1, Issue 2

127 -- 151Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli. Removing communications in clustered microarchitectures through instruction replication
152 -- 179Yu Bai, R. Iris Bahar. A low-power in-order/out-of-order issue queue
180 -- 219Philo Juang, Kevin Skadron, Margaret Martonosi, Zhigang Hu, Douglas W. Clark, Phil Diodato, Stefanos Kaxiras. Implementing branch-predictor decay using quasi-static memory cells
220 -- 245Oliverio J. Santana, Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero. A low-complexity fetch architecture for high-performance superscalar processors

Volume 1, Issue 1

1 -- 2Brad Calder, Dean M. Tullsen. Introduction
3 -- 33Wei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. Reducing instruction cache energy consumption using a compiler-based strategy
34 -- 61Nemanja Isailovic, Mark Whitney, Yatish Patel, John Kubiatowicz, Dean Copsey, Frederic T. Chong, Isaac L. Chuang, Mark Oskin. Datapath and control for quantum wires
62 -- 93Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Nitya Ranganathan, Doug Burger, Stephen W. Keckler, Robert G. McDonald, Charles R. Moore. TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP
94 -- 125Kevin Skadron, Mircea R. Stan, Karthik Sankaranarayanan, Wei Huang, Sivakumar Velusamy, David Tarjan. Temperature-aware microarchitecture: Modeling and implementation