| 401 | -- | 424 | Jerry R. Burch, Edmund M. Clarke, David E. Long, Kenneth L. McMillan, David L. Dill. Symbolic model checking for sequential circuit verification |
| 425 | -- | 438 | Taewhan Kim, Noritake Yonezawa, Jane W.-S. Liu, C. L. Liu. A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach |
| 439 | -- | 450 | Tsing-Fa Lee, Allen C.-H. Wu, Youn-Long Lin, Daniel D. Gajski. A transformation-based method for loop folding |
| 451 | -- | 458 | Minjoong Rim, Rajiv Jain. Lower-bound performance estimation for the high-level synthesis scheduling problem |
| 459 | -- | 470 | Mark Aagaard, Miriam Leeser. PBS: proven Boolean simplification |
| 471 | -- | 481 | Ahmed S. Desouki, Young-June Park, Hong-Shick Min. A CAD procedure for optimizing bipolar devices relative to BiCMOS circuit delays |
| 482 | -- | 493 | Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury. Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices |
| 494 | -- | 506 | Rupert Howes, William Redman-White, Ken G. Nichols, Peter J. Mole, Michael J. Robinson, Simon Bird. An SOS MOSFET model based on calculation of the surface potential |
| 507 | -- | 514 | Tatsuya Kunikiyo, Katsuyoshi Mitsui, Masato Fujinaga, Tetsuya Uchida, Norihiko Kotani. Reverse short-channel effect due to lateral diffusion of point-defect induced by source/drain ion implantation |
| 515 | -- | 530 | Henry Cox, Janusz Rajski. On necessary and nonconflicting assignments in algorithmic test pattern generation |
| 531 | -- | 535 | Noriyuki Takahashi, Nagisa Ishiura, Shuzo Yajima. Fault simulation for multiple faults by Boolean function manipulation |