| 1309 | -- | 1318 | Ganesh Gopalakrishnan, Erik Brunvand, Nick Michell, Steven M. Nowick. A correctness criterion for asynchronous circuit validation and optimization |
| 1319 | -- | 1332 | Amir H. Farrahi, Majid Sarrafzadeh. Complexity of the lookup-table minimization problem for FPGA technology mapping |
| 1333 | -- | 1350 | S. Parameswaran, M. F. Schulz. Computer-aided selection of components for technology-independent specifications |
| 1351 | -- | 1365 | Jeff Griffith, Gabriel Robins, Jeffrey S. Salowe, Tongtong Zhang. Closing the gap: near-optimal Steiner trees in polynomial time |
| 1366 | -- | 1378 | Dirk Theune, Ralf Thiele, W. John, Thomas Lengauer. Robust methods for EMC-driven routing |
| 1379 | -- | 1390 | M. Karim Moallemi, Hui Zhang. A general numerical procedure for multilayer multistep IC process simulation |
| 1391 | -- | 1399 | Giorgio Casinovi, Jeen-Mo Yang. Multi-level simulation of large analog systems containing behavioral models |
| 1400 | -- | 1408 | Alberto Leone, Antonio Gnudi, Giorgio Baccarani. Hydrodynamic simulation of semiconductor devices operating at low temperature |
| 1409 | -- | 1412 | Jun-Fa Mao, Zheng-Fan Li. Waveform relaxation solution of the ABCD matrices of nonuniform transmission lines for transient analysis |
| 1413 | -- | 1418 | S. Wayne Bollinger, Scott F. Midkiff. Test generation for I::DDQ:: testing of bridging faults in CMOS circuits |
| 1418 | -- | 1425 | Richard I. Hartley, Albert E. Casavant. Optimizing pipelined networks of associative and commutative operators |
| 1425 | -- | 1428 | Akira Kato, Mitsutaka Katada, Toyoharu Kamiya, Toyoki Ito, Tadashi Hattori. A rapid, stable decoupled algorithm for solving semiconductor hydrodynamic equations |
| 1428 | -- | 1434 | Irith Pomeranz, Sudhakar M. Reddy. On determining symmetries in inputs of logic circuits |
| 1434 | -- | 1437 | Yasunori Sameshima, Yoshihiro Kitamura, Tomoo Fukazawa. Multiple signature analysis method using fault simulation |