| 1073 | -- | 1087 | Arun Achyuthan, Mohamed I. Elmasry. Mixed analog/digital hardware synthesis of artificial neural networks |
| 1088 | -- | 1096 | Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien. Spectral K-way ratio-cut partitioning and clustering |
| 1097 | -- | 1109 | Brian Lockyear, Carl Ebeling. Optimal retiming of level-clocked circuits using symmetric clock schedules |
| 1110 | -- | 1122 | Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain. Power efficient technology decomposition and mapping under an extended power consumption model |
| 1123 | -- | 1131 | Farid N. Najm. Low-pass filter for computing the transition density in digital circuits |
| 1132 | -- | 1142 | Sherif H. K. Embabi, R. Damodaran. Delay models for CMOS, BiCMOS and BiNMOS circuits and their applications for timing simulations |
| 1143 | -- | 1158 | Wolfgang Kunz, Dhiraj K. Pradhan. Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization |
| 1159 | -- | 1166 | Tai-Yu Chou, Zoltan J. Cendes. Capacitance calculation of IC packages using the finite element method and planes of symmetry |
| 1166 | -- | 1170 | Sudhir M. Gowda, Bing J. Sheu. BSIM plus: an advanced SPICE model for submicron MOS VLSI circuits |
| 1170 | -- | 1178 | Dimitrios Kagaris, Fillia Makedon, Spyros Tragoudas. A method for pseudo-exhaustive test pattern generation |
| 1179 | -- | 1184 | Ted Stanion, Carl Sechen. Boolean division and factorization using binary decision diagrams |