| 1189 | -- | 1200 | Konrad Doll, Frank M. Johannes, Kurt Antreich. Iterative placement improvement by network flow methods |
| 1201 | -- | 1222 | King C. Ho, Sarma B. K. Vrudhula. Interval graph algorithms for two-dimensional multiple folding of array-based VLSI layouts |
| 1223 | -- | 1234 | Ping-Chung Li, Georgios I. Stamoulis, Ibrahim N. Hajj. A probabilistic timing approach to hot-carrier effect estimation |
| 1235 | -- | 1240 | Minchang Liang, Mark E. Law. An object-oriented approach to device simulation-FLOODS |
| 1241 | -- | 1246 | Dwight L. Woolard, Hong Tian, Michael A. Littlejohn, K. W. Kim. The implementation of physical boundary conditions in the Monte Carlo simulation of electron devices |
| 1247 | -- | 1256 | Walter Allegretto, Bing Shen, P. Haswell, Zhongsheng Lai, Alexander M. Robinson. Numerical modeling of a micromachined thermal conductivity gas pressure sensor |
| 1257 | -- | 1270 | Seok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage. Time-domain macromodels for VLSI interconnect analysis |
| 1271 | -- | 1279 | Abdolreza Nabavi-Lishi, Nicholas C. Rumin. Inverter models of CMOS gates for supply current and delay evaluation |
| 1280 | -- | 1287 | TingTing Hwang, Robert Michael Owens, Mary Jane Irwin, Kuo-Hua Wang. Logic synthesis for field-programmable gate arrays |
| 1288 | -- | 1300 | Jaushin Lee, Janak H. Patel. Architectural level test generation for microprocessors |
| 1301 | -- | 1305 | T. V. Nguyen. Recursive convolution and discrete time domain simulation of lossy coupled transmission lines |