669 | -- | 683 | Jan M. Rabaey, Miodrag Potkonjak. Estimating implementation bounds for real time DSP application specific circuits |
684 | -- | 693 | Tae Won Cho, Sam S. Pyo, J. Robert Heath. PARALLEX: a parallel approach to switchbox routing |
694 | -- | 701 | Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri. Block placement with a Boltzmann Machine |
702 | -- | 711 | Y. Apanovich, Eugeny D. Lyumkis, Boris S. Polsky, Alex I. Shur, Peter A. Blakey. Steady-state and transient analysis of submicron devices using energy balance and simplified hydrodynamic models |
712 | -- | 724 | Udaya A. Ranawake, Carl Huster, Patrick M. Lenders, Stephen Marshall Goodnick. PMC-3D: a parallel three-dimensional Monte Carlo semiconductor device simulator |
725 | -- | 728 | Jason Yao-Tsung Tsai, Kuo-Don Hong, Yin-Lun Yuan. An efficient analytical model for calculating trapped charge in amorphous silicon |
729 | -- | 736 | Demos F. Anastasakis, Nanda Gopal, Seok-Yoon Kim, Lawrence T. Pillage. Enhancing the stability of asymptotic waveform evaluation for digital interconnect circuit applications |
737 | -- | 745 | Sina Balkir, Mehmet Yanilmaz, Martin A. Plonus. Numerical integration using Bezier splines |
746 | -- | 762 | Anirudh Devgan, Ronald A. Rohrer. Adaptively controlled explicit simulation |
763 | -- | 776 | Curtis L. Ratzlaff, Lawrence T. Pillage. RICE: rapid interconnect circuit evaluation using AWE |
777 | -- | 785 | Chung-Hsing Chen, Tanay Karnik, Daniel G. Saab. Structural and behavioral synthesis for testability techniques |
786 | -- | 795 | Silvano Gai, Pier Luca Montessoro. Creator: new advanced concepts in concurrent simulation |
796 | -- | 813 | Linda S. Milor, Alberto L. Sangiovanni-Vincentelli. Minimizing production test time to detect faults in analog circuits |
814 | -- | 822 | Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang. Event suppression: improving the efficiency of timing simulation for synchronous digital circuits |
822 | -- | 826 | Hsu-Chun Yen. On multiterminal single bend wirability |