| 277 | -- | 292 | Miodrag Potkonjak, Jan M. Rabaey. Optimizing resource utilization using transformations |
| 293 | -- | 302 | Philip B. M. Wolbert, Gerhard K. M. Wachutka, Benno H. Krabbenborg, Ton J. Mouthaan. Nonisothermal device simulation using the 2D numerical process/device simulator TRENDY and application to SOI-devices |
| 303 | -- | 309 | Ting-Hai Chao, Yu-Chin Hsu. Rectilinear Steiner tree construction by local and global refinement |
| 310 | -- | 317 | Ronald J. G. Goossens, Stephen G. Beebe, Zhiping Yu, Robert W. Dutton. An automatic biasing scheme for tracing arbitrarily shaped I-V curves |
| 318 | -- | 337 | Shiang-Tang Huang, Tai-Ming Parng, Jyuo-Min Shyu. Timed Boolean calculus and its applications in timing analysis |
| 338 | -- | 352 | Peter M. Maurer, Yun Sik Lee. Gateways: a technique for adding event-driven behavior to compiled simulations |
| 353 | -- | 358 | Bechir Ayari, Bozena Kaminska. A new dynamic test vector compaction for automatic test pattern generation |
| 359 | -- | 369 | Víctor H. Champac, Antonio Rubio, Joan Figueras. Electrical model of the floating gate defect in CMOS ICs: implications on I::DDQ:: testing |
| 370 | -- | 377 | Beyin Chen, Chung-Len Lee. A complement-based fast algorithm to generate universal test sets for multi-output functions |
| 378 | -- | 386 | Irith Pomeranz, Sudhakar M. Reddy. On achieving complete fault coverage for sequential machines |
| 387 | -- | 395 | Antonio Rubio, Noriyoshi Itazaki, Xiaole Xu, Kozo Kinoshita. An approach to the analysis and detection of crosstalk faults in digital VLSI circuits |
| 396 | -- | 397 | Russell Kao, Mark Horowitz. Eliminating redundant DC equations for asymptotic waveform evaluation |