| 537 | -- | 552 | Said Amellal, Bozena Kaminska. Functional synthesis of digital systems with TASS |
| 553 | -- | 565 | Daniel Brand, Vijay S. Iyengar. Identification of redundant delay faults |
| 566 | -- | 580 | Kaushik De, Balkrishna Ramkumar, Prithviraj Banerjee. A portable parallel algorithm for logic synthesis using transduction |
| 581 | -- | 588 | P. N. Lam, Hon F. Li, S. C. Leung. Optimization of state encoding in distributed circuits |
| 589 | -- | 602 | Alexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. Satisfaction of input and output encoding constraints |
| 603 | -- | 609 | C. Y. Roger Chen, Cliff Yungchin Hou, Uminder Singh. Optimal algorithms for bubble sort based non-Manhattan channel routing |
| 610 | -- | 615 | Mitiko Miura-Mattausch. Analytical MOSFET model for quarter micron technologies |
| 616 | -- | 624 | Kenny K. H. Toh, Andrew R. Neureuther, Edward W. Scheckler. Algorithms for simulation of three-dimensional etching |
| 625 | -- | 637 | Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer. SWiTEST: a switch level test generation system for CMOS combinational circuits |
| 638 | -- | 646 | Weiwei Mao, Michael D. Ciletti. Reducing correlation to improve coverage of delay faults in scan-path design |
| 638 | -- | 0 | Kuo-Feng Liao, Majid Sarrafzadeh. Correction to Boundary single-layer routing with movable terminals |
| 646 | -- | 651 | Premachandran R. Menon, Hitesh Ahuja, Mohan Harihara. Redundancy identification and removal in combinational circuits |
| 651 | -- | 658 | Michael Nicolaidis. Fault secure property versus strongly code disjoint checkers |
| 658 | -- | 664 | Janusz A. Starzyk. Hierarchical analysis of high frequency interconnect networks |