| 1061 | -- | 1076 | Supratik Chakraborty, Kenneth Y. Yun, David L. Dill. Timing analysis of asynchronous systems using time separation of events |
| 1077 | -- | 1095 | Peter Voigt Knudsen, Jan Madsen. Integrating communication protocol selection with hardware/software codesign |
| 1096 | -- | 1106 | Shih-Chieh Chang, David Ihsin Cheng. Efficient Boolean division and substitution using redundancy addition and removing |
| 1107 | -- | 1113 | Scott Hauck, Zhiyuan Li, Eric J. Schwabe. Configuration compression for the Xilinx XC6200 FPGA |
| 1114 | -- | 1131 | Anand Raghunathan, Sujit Dey, Niraj K. Jha. Register transfer level power optimization with emphasis on glitch analysis and reduction |
| 1132 | -- | 1150 | Kenneth L. Shepard, Vinod Narayanan, Ron Rose. Harmony: static noise analysis of deep submicron digital integrated circuits |
| 1151 | -- | 1164 | Moshe Meyassed, Robert H. Klenke, James H. Aylor. Resolving unknown inputs in mixed-level simulation with sequential elements |
| 1165 | -- | 1177 | Yoshihiro Yamagami, Yoshifumi Nishio, Akio Ushida, Masayuki Takahashi, Kimihiro Ogawa. Analysis of communication circuits based on multidimensional Fourier transformation |
| 1178 | -- | 1191 | Rajesh Pendurkar, Craig A. Tovey, Abhijit Chatterjee. Single-probe traversal optimization for testing of MCM substrate interconnections |
| 1192 | -- | 1201 | Qian-Yu Tang, Xiaoyu Song, Yuke Wang. Diagnosis of clustered faults for identical degree topologies |
| 1202 | -- | 1213 | Nur A. Touba, Edward J. McCluskey. RP-SYN: synthesis of random pattern testable circuits with test point insertion |
| 1214 | -- | 1219 | Abbas Seifi, Kumaraswamy Ponnambalam, Jiri Vlach. Probabilistic design of integrated circuits with correlated input parameters |