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    Journal: IEEE Trans. on CAD of Integrated Circuits and Systems

    Volume 18, Issue 9

    1221 -- 1236Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev. Decomposition and technology mapping of speed-independent circuits using Boolean relations
    1237 -- 1248Morgan Enos, Scott Hauck, Majid Sarrafzadeh. Evaluation and optimization of replication algorithms for logic bipartitioning
    1249 -- 1264Naresh Maheshwari, Sachin S. Sapatnekar. Optimizing large multiphase level-clocked circuits
    1265 -- 1278Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky. On wirelength estimations for row-based placement
    1279 -- 1296Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta. Extraction of functional regularity in datapath circuits
    1297 -- 1304Chris C. N. Chu, Martin D. F. Wong. An efficient and optimal algorithm for simultaneous buffer and wire sizing
    1305 -- 1315Amir H. Salek, Jinan Lou, Massoud Pedram. An integrated logical and physical design flow for deep submicron circuits
    1316 -- 1326Darko Kirovski, Chunho Lee, Miodrag Potkonjak, William H. Mangione-Smith. Application-driven synthesis of memory-intensive systems-on-chip
    1327 -- 1340Samir Boubezari, Eduard Cerny, Bozena Kaminska, Benoit Nadeau-Dostie. Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST
    1341 -- 1352Shi-Yu Huang, Kwang-Ting Cheng. ErrorTracer: design error diagnosis based on fault simulation techniques
    1353 -- 1368Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich. Analog testing by characteristic observation inference
    1369 -- 1375Massimo Alioto, Gaetano Palumbo. Highly accurate and simple models for CML and ECL gates
    1376 -- 1384Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng. AutoFix: a hybrid tool for automatic logic rectification
    1385 -- 1389Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang. Slicing floorplans with boundary constraints
    1389 -- 1399Jason Y. Zien, Martine D. F. Schlag, Pak K. Chan. Multilevel spectral hypergraph partitioning with arbitrary vertex sizes
    1400 -- 1401K. C. Chang. Comment on Event suppression by optimizing VHDL programs

    Volume 18, Issue 8

    1061 -- 1076Supratik Chakraborty, Kenneth Y. Yun, David L. Dill. Timing analysis of asynchronous systems using time separation of events
    1077 -- 1095Peter Voigt Knudsen, Jan Madsen. Integrating communication protocol selection with hardware/software codesign
    1096 -- 1106Shih-Chieh Chang, David Ihsin Cheng. Efficient Boolean division and substitution using redundancy addition and removing
    1107 -- 1113Scott Hauck, Zhiyuan Li, Eric J. Schwabe. Configuration compression for the Xilinx XC6200 FPGA
    1114 -- 1131Anand Raghunathan, Sujit Dey, Niraj K. Jha. Register transfer level power optimization with emphasis on glitch analysis and reduction
    1132 -- 1150Kenneth L. Shepard, Vinod Narayanan, Ron Rose. Harmony: static noise analysis of deep submicron digital integrated circuits
    1151 -- 1164Moshe Meyassed, Robert H. Klenke, James H. Aylor. Resolving unknown inputs in mixed-level simulation with sequential elements
    1165 -- 1177Yoshihiro Yamagami, Yoshifumi Nishio, Akio Ushida, Masayuki Takahashi, Kimihiro Ogawa. Analysis of communication circuits based on multidimensional Fourier transformation
    1178 -- 1191Rajesh Pendurkar, Craig A. Tovey, Abhijit Chatterjee. Single-probe traversal optimization for testing of MCM substrate interconnections
    1192 -- 1201Qian-Yu Tang, Xiaoyu Song, Yuke Wang. Diagnosis of clustered faults for identical degree topologies
    1202 -- 1213Nur A. Touba, Edward J. McCluskey. RP-SYN: synthesis of random pattern testable circuits with test point insertion
    1214 -- 1219Abbas Seifi, Kumaraswamy Ponnambalam, Jiri Vlach. Probabilistic design of integrated circuits with correlated input parameters

    Volume 18, Issue 7

    869 -- 888Aiguo Xie, Peter A. Beerel. Accelerating Markovian analysis of asynchronous systems using state compression
    889 -- 902Arun N. Lokanathan, Jay B. Brockman. A methodology for concurrent process-circuit optimization
    903 -- 917Henrik Hulgaard, Poul Frederick Williams, Henrik Reif Andersen. Equivalence checking of combinational circuits using Boolean expression diagrams
    918 -- 935Manish Pandey, Randal E. Bryant. Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation
    936 -- 955Sheetanshu L. Pandey, Kothanda Umamageswaran, Philip A. Wilsey. VHDL semantics and validating transformations
    956 -- 972Sofiène Tahar, Xiaoyu Song, Eduard Cerny, Zijian Zhou, Michel Langevin, Otmane Aït Mohamed. Modeling and formal verification of the Fairisle ATM switch fabricusing MDGs
    973 -- 993Radu Marculescu, Diana Marculescu, Massoud Pedram. Sequence compaction for power estimation: theory and practice
    994 -- 999Youxin Gao, Martin D. F. Wong. Optimal shape function for a bidirectional wire under Elmore delay model
    1000 -- 1013Christoph Maier, Markus Emmenegger, Stefano Taschini, Henry Baltes, Jan G. Korvink. Equivalent circuit model of resistive IC sensors derived with the box integration method
    1014 -- 1025Chung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong. Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
    1026 -- 1039Giri Devarayanadurg, Mani Soma, Prashant Goteti, Sam D. Huynh. Test set selection for structural faults in analog IC s
    1040 -- 1049Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo. Static test compaction for synchronous sequential circuits based on vector restoration
    1050 -- 1057Spyros Tragoudas, Dimitrios Karayiannis. A fast nonenumerative automatic test pattern generator for pathdelay faults

    Volume 18, Issue 6

    669 -- 684Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar. Primitive delay faults: identification, testing, and design for testability
    685 -- 696Ben Mathew, Daniel G. Saab. Combining multiple DFT schemes with test generation
    697 -- 713Mahadevamurty Nemani, Farid N. Najm. High-level area and power estimation for VLSI circuits
    714 -- 725Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy. Models and algorithms for bounds on leakage in CMOS circuits
    726 -- 741Catherine H. Gebotys. A minimum-cost circulation approach to DSP address-code generation
    742 -- 760Alain Girault, Bilung Lee, Edward A. Lee. Hierarchical finite state machines with multiple concurrency models
    761 -- 768Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey. An output encoding problem and a solution technique
    769 -- 786Chris J. Myers, Tomas Rokicki, Teresa H. Y. Meng. POSET timing and its application to the synthesis and verification of gate-level timed circuits
    787 -- 798Chris C. N. Chu, Martin D. F. Wong. A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing
    799 -- 812Hirendu Vaishnav, Massoud Pedram. Delay-optimal clustering targeting low-power VLSI circuits
    813 -- 833Luca Benini, Alessandro Bogliolo, Giuseppe A. Paleologo, Giovanni De Micheli. Policy optimization for dynamic power management
    834 -- 849Felice Balarin, Massimiliano Chiodo, Paolo Giusto, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli, Ellen Sentovich, Kei Suzuki. Synthesis of software programs for embedded control applications
    850 -- 861Sanghyeon Baeg, William A. Rogers. A cost-effective design for testability: clock line control and test generation using selective clocking
    861 -- 868Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik. Using configurable computing to accelerate Boolean satisfiability

    Volume 18, Issue 5

    505 -- 523Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha. Wavesched: a novel scheduling technique for control-flow intensive designs
    524 -- 532Miodrag Potkonjak, Jan M. Rabaey. Algorithm selection: a quantitative optimization-intensive approach
    533 -- 544Sven Wuytack, Julio Leao da Silva Jr., Francky Catthoor, Gjalt G. de Jong, Chantal Ykman-Couvreur. Memory management for embedded network applications
    545 -- 556Gianpiero Cabodi, Paolo Camurati, Stefano Quer. Improving the efficiency of BDD-based operators by means of partitioning
    557 -- 575Alexander Chatzigeorgiou, Spiridon Nikolaidis, Ioannis Tsoukalas. A modeling technique for CMOS gates
    576 -- 581J. Joseph Clement, Stefan P. Riege, Radenko Cvijetic, Carl V. Thompson. Methodology for electromigration critical threshold design rule evaluation
    582 -- 596Massimo Conti, Paolo Crippa, Simone Orcioni, Claudio Turchetti. Parametric yield formulation of MOS IC s affected by mismatch effect
    597 -- 607Joao Paulo Costa, Mike Chou, Luis Miguel Silveira. Efficient techniques for accurate modeling and simulation ofsubstrate coupling in mixed-signal IC s
    608 -- 620Chin-Chih Chang, Jason Cong. An efficient approach to multilayer layer assignment with anapplication to via minimization
    621 -- 630Srimat T. Chakradhar, Sujit Dey. Resynthesis and retiming for optimum partial scan
    631 -- 644Laurence Goodby, Alex Orailoglu. Redundancy and testability in digital filter datapaths
    645 -- 658David Van Campenhout, Trevor N. Mudge, Karem A. Sakallah. Timing verification of sequential dynamic circuits
    659 -- 665Young-Jun Cha, Chong S. Rim, Kazuo Nakajima. SEGRA: a very fast general area router for multichip modules
    665 -- 666Irith Pomeranz, Sudhakar M. Reddy. A comment on Improving a nonenumerative method to estimate path delay fault coverage

    Volume 18, Issue 4

    375 -- 388Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley. Device-level early floorplanning algorithms for RF circuits
    389 -- 397Kia Bazargan, Samjung Kim, Majid Sarrafzadeh. Nostradamus: a floorplanner of uncertain designs
    398 -- 405Chris C. N. Chu, Martin D. F. Wong. Greedy wire-sizing is linear time
    406 -- 420Jason Cong, Lei He. Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing
    421 -- 435Shantanu Dutt, Hasan Arslan, Halim Theny. Partitioning using second-order information and stochastic-gainfunctions
    436 -- 444Huibo Hou, Jiang Hu, Sachin S. Sapatnekar. Non-Hanan routing
    445 -- 462Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky. Filling algorithms and analyses for layout density control
    463 -- 474Evanthia Papadopoulou, D. T. Lee. Critical area computation via Voronoi diagrams
    475 -- 483Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin. A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning
    484 -- 493Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng. Sequence-pair approach for rectilinear module placement
    494 -- 501Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas. An algorithm for determining repetitive patterns in very large IC layouts

    Volume 18, Issue 3

    253 -- 264Joseph A. Fernando, Jack S. N. Jean. Processor array design with FPGA area constraint
    265 -- 281Ganesh Lakshminarayana, Niraj K. Jha. High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors
    282 -- 292Chih-Chang Lin, Kuang-Chien Chen, Malgorzata Marek-Sadowska. Logic synthesis for engineering change
    293 -- 300Mustafa Celik, Lawrence T. Pileggi. Metrics and bounds for phase delay and signal attenuation in RC(L)clock trees
    301 -- 310Edoardo Charbon, Paolo Miliozzi, Luca P. Carloni, Alberto Ferrari, Alberto L. Sangiovanni-Vincentelli. Modeling digital substrate noise injection in mixed-signal IC s
    311 -- 321Michael W. Beattie, Lawrence T. Pileggi. Error bounds for capacitance extraction via window techniques
    322 -- 331John Lillis, Chung-Kuan Cheng. Timing optimization for multisource nets: characterization andoptimal repeater insertion
    332 -- 345Abdessatar Abderrahman, Eduard Cerny, Bozena Kaminska. Worst case tolerance analysis and CLP-based multifrequency test generation for analog circuits
    346 -- 356Brian Chess, Tracy Larrabee. Creating small fault dictionaries [logic circuit fault diagnosis]
    357 -- 370Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha. Hierarchical test generation and design for testability methods for ASPPs and ASIPs

    Volume 18, Issue 2

    81 -- 100Christoph Scholl, Dirk Möller, Paul Molitor, Rolf Drechsler. BDD minimization using symmetries
    101 -- 117Kenneth Y. Yun, David L. Dill. Automatic synthesis of extended burst-mode circuits. I.(Specification and hazard-free implementations)
    118 -- 132Kenneth Y. Yun, David L. Dill. Automatic synthesis of extended burst-mode circuits. II. (Automaticsynthesis)
    133 -- 141Zhaojun Bai, Rodney D. Slone, William T. Smith, Qiang Ye. Error bound for reduced system model by Pade approximation via the Lanczos process
    142 -- 150Toshiyuki Hama, Hiroaki Etoh. Topological routing path search algorithm with incremental routability test
    151 -- 162Witold A. Pleskacz, Charles H. Ouyang, Wojciech Maly. A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits
    163 -- 171Jin-Tai Yan. An improved optimal algorithm for bubble-sorting-basednon-Manhattan channel routing
    172 -- 190Edoardo Charbon, Ranjit Gharpurey, Robert G. Meyer, Alberto L. Sangiovanni-Vincentelli. Substrate optimization based on semi-analytical techniques
    191 -- 202Fulvio Corno, Uwe Gläser, Paolo Prinetto, Matteo Sonza Reorda, Heinrich Theodor Vierhaus, Massimo Violante. SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information
    203 -- 211Yuejian Wu, Saman Adham. Scan-based BIST fault diagnosis
    212 -- 219Atul Garg, Y. L. Le Coz, Hans J. Greub, R. B. Iverson, Robert F. Philhower, Pete M. Campbell, Cliff A. Maier, Sam A. Steidl, Matthew W. Ernest, Russell P. Kraft, Steven R. Carlough, J. W. Perry, Thomas W. Krawczyk Jr., John F. McDonald. Accurate high-speed performance prediction for full differential current-mode logic: the effect of dielectric anisotropy
    219 -- 230Dimitrios Kagaris, Spyros Tragoudas. On the design of optimal counter-based schemes for test set embedding
    231 -- 238How-Rern Lin, TingTing Hwang. On determining sensitization criterion in an iterative gate sizing process
    238 -- 247Dhiraj K. Pradhan, Mitrajit Chatterjee. GLFSR-a new test pattern generator for built-in-self-test
    248 -- 251Armen H. Zemanian, Victor A. Chang. Exterior templates for capacitance computations [interconnections]

    Volume 18, Issue 12

    1689 -- 1701Haris Lekatsas, Wayne Wolf. SAMC: a code compression algorithm for embedded processors
    1702 -- 1714Inki Hong, Darko Kirovski, Gang Qu, Miodrag Potkonjak, Mani B. Srivastava. Power optimization of variable-voltage core-based systems
    1715 -- 1729Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha. High-level synthesis of low-power control-flow intensive circuits
    1730 -- 1740Alfredo J. Piazza, Can E. Korman, Amro M. Jaradeh. A physics-based semiconductor noise model suitable for efficient numerical implementation
    1741 -- 1749Wolfgang Pyka, Peter Fleischmann, Bernhard Haindl, Siegfried Selberherr. Three-dimensional simulation of HPCVD-linking continuum transport and reaction kinetics with topography simulation
    1750 -- 1758Alexandre Linhares, Horacio Hideki Yanasse, José Ricardo de Almeida Torreao. Linear gate assignment: a fast statistical mechanics approach
    1759 -- 1767Youxin Gao, Martin D. F. Wong. Wire-sizing optimization with inductance consideration using transmission-line model
    1768 -- 1779Haluk Konuk. Voltage- and current-based fault simulation for interconnect open defects
    1780 -- 1792Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth. A synthesis for testability scheme for finite state machines using clock control
    1793 -- 1802Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang. Broadcasting test patterns to multiple circuits
    1803 -- 1816Andreas G. Veneris, Ibrahim N. Hajj. Design error diagnosis and correction via test vector simulation
    1817 -- 1824Ashok Vittal, Lauren Hui Chen, Malgorzata Marek-Sadowska, Kai-Ping Wang, Sherry Yang. Crosstalk in VLSI interconnections

    Volume 18, Issue 11

    1529 -- 1541Darko Kirovski, Miodrag Potkonjak, Lisa M. Guerra. Improving the observability and controllability of datapaths foremulation-based debugging
    1542 -- 1557Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell. An efficient filter-based approach for combinational verification
    1558 -- 1565Asen Asenov, Andrew R. Brown, John H. Davies, Subhash Saini. Hierarchical approach to atomistic 3-D MOSFET simulation
    1566 -- 1576Mario Netzel, Bernd Heinemann, Maik Brett, Dagmar Schipanski. Methods for generating and editing merged isotropic/anisotropic triangular-element meshes
    1577 -- 1594Ganesh Lakshminarayana, Niraj K. Jha. FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions
    1595 -- 1607Jason Cong, Chang Wu. Optimal FPGA mapping and retiming with efficient initial state computation
    1608 -- 1618David L. Harris, Mark Horowitz, Dean Liu. Timing analysis including clock skew
    1619 -- 1632Jorge M. Pena, Arlindo L. Oliveira. A new algorithm for exact reduction of incompletely specified finite state machines
    1633 -- 1645Charles J. Alpert, Anirudh Devgan, Stephen T. Quay. Buffer insertion for noise and delay optimization
    1646 -- 1653Toshiyuki Hama, Hiroaki Etoh. Curvilinear detailed routing with simultaneous wire-spreading and wire-fattening
    1654 -- 1660Hany L. Abdel-Malek, Abdel-Karim S. O. Hassan, Mohamed H. Heaba. A boundary gradient search technique and its applications in design centering
    1661 -- 1676Indradeep Ghosh, Niraj K. Jha, Sujit Dey. A low overhead design for testability and test generation technique for core-based systems-on-a-chip
    1676 -- 1683Von-Kyoung Kim, Tom Chen. On comparing functional fault coverage and defect coverage for memory testing
    1683 -- 1688Hai Zhou, Martin D. F. Wong. Global routing with crosstalk constraints

    Volume 18, Issue 10

    1405 -- 1417Yanbing Li, Wayne Wolf. Hardware/software co-synthesis with memory hierarchies
    1418 -- 1434Wei-Chun Chou, Peter A. Beerel, Kenneth Y. Yun. Average-case technology mapping of asynchronous burst-mode circuits
    1435 -- 1441Hoan H. Pham, Arokia Nathan. An integral equation of the second kind for computation of capacitance
    1442 -- 1451Le-Chin Eugene Liu, Carl Sechen. Multilayer chip-level global routing using an efficient graph-based Steiner tree heuristic
    1452 -- 1461Le-Chin Eugene Liu, Carl Sechen. Multilayer pin assignment for macro cell circuits
    1462 -- 1479Hsiao-Ping Tseng, Carl Sechen. A gridless multilayer router for standard cell circuits using CTMcells
    1480 -- 1486Gerard A. Allan, Anthony J. Walton. Efficient extra material critical area algorithms
    1487 -- 1495Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai. Fault emulation: A new methodology for fault grading
    1496 -- 1508Sujit Dey, Anand Raghunathan, Niraj K. Jha, Kazutoshi Wakabayashi. Controller-based power management for control-flow intensive designs
    1508 -- 1511Mahesh B. Patil. Extension of the VR discretization scheme for velocity saturation
    1512 -- 1519Massoud Pedram, Bryan Preas. Interconnection analysis for standard cell layouts
    1519 -- 1526Jin-Tai Yan. An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing ordering
    1527 -- 1527Robert P. Dick, Niraj K. Jha. Corrections to mogac: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems

    Volume 18, Issue 1

    1 -- 2Gaetano Borriello, Diederik Verkest, Francky Catthoor. Guest Editorial
    3 -- 13Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau. Local memory exploration and optimization in embedded systems
    14 -- 24Uwe Eckhardt, Renate Merker. Hierarchical algorithm partitioning at system level for an improved utilization of memory structures
    25 -- 32Christian Blumenröhr, Dirk Eisenbiegler, Detlef Schmid. On the efficiency of formal synthesis-experimental results
    33 -- 43Henning Dierks. Synthesizing controllers from real-time specifications
    44 -- 57Bart Mesman, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess. Constraint analysis for DSP code generation
    58 -- 68Robert Pasko, Patrick Schaumont, Veerle Derudder, Serge Vernalde, Daniela Durackova. A new algorithm for elimination of common subexpressions
    69 -- 75Frank Vahid. Techniques for minimizing and balancing I/O during functional partitioning
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