| 869 | -- | 888 | Aiguo Xie, Peter A. Beerel. Accelerating Markovian analysis of asynchronous systems using state compression |
| 889 | -- | 902 | Arun N. Lokanathan, Jay B. Brockman. A methodology for concurrent process-circuit optimization |
| 903 | -- | 917 | Henrik Hulgaard, Poul Frederick Williams, Henrik Reif Andersen. Equivalence checking of combinational circuits using Boolean expression diagrams |
| 918 | -- | 935 | Manish Pandey, Randal E. Bryant. Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation |
| 936 | -- | 955 | Sheetanshu L. Pandey, Kothanda Umamageswaran, Philip A. Wilsey. VHDL semantics and validating transformations |
| 956 | -- | 972 | Sofiène Tahar, Xiaoyu Song, Eduard Cerny, Zijian Zhou, Michel Langevin, Otmane Aït Mohamed. Modeling and formal verification of the Fairisle ATM switch fabricusing MDGs |
| 973 | -- | 993 | Radu Marculescu, Diana Marculescu, Massoud Pedram. Sequence compaction for power estimation: theory and practice |
| 994 | -- | 999 | Youxin Gao, Martin D. F. Wong. Optimal shape function for a bidirectional wire under Elmore delay model |
| 1000 | -- | 1013 | Christoph Maier, Markus Emmenegger, Stefano Taschini, Henry Baltes, Jan G. Korvink. Equivalent circuit model of resistive IC sensors derived with the box integration method |
| 1014 | -- | 1025 | Chung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong. Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation |
| 1026 | -- | 1039 | Giri Devarayanadurg, Mani Soma, Prashant Goteti, Sam D. Huynh. Test set selection for structural faults in analog IC s |
| 1040 | -- | 1049 | Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo. Static test compaction for synchronous sequential circuits based on vector restoration |
| 1050 | -- | 1057 | Spyros Tragoudas, Dimitrios Karayiannis. A fast nonenumerative automatic test pattern generator for pathdelay faults |