Journal: IEEE Trans. on CAD of Integrated Circuits and Systems

Volume 18, Issue 2

81 -- 100Christoph Scholl, Dirk Möller, Paul Molitor, Rolf Drechsler. BDD minimization using symmetries
101 -- 117Kenneth Y. Yun, David L. Dill. Automatic synthesis of extended burst-mode circuits. I.(Specification and hazard-free implementations)
118 -- 132Kenneth Y. Yun, David L. Dill. Automatic synthesis of extended burst-mode circuits. II. (Automaticsynthesis)
133 -- 141Zhaojun Bai, Rodney D. Slone, William T. Smith, Qiang Ye. Error bound for reduced system model by Pade approximation via the Lanczos process
142 -- 150Toshiyuki Hama, Hiroaki Etoh. Topological routing path search algorithm with incremental routability test
151 -- 162Witold A. Pleskacz, Charles H. Ouyang, Wojciech Maly. A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits
163 -- 171Jin-Tai Yan. An improved optimal algorithm for bubble-sorting-basednon-Manhattan channel routing
172 -- 190Edoardo Charbon, Ranjit Gharpurey, Robert G. Meyer, Alberto L. Sangiovanni-Vincentelli. Substrate optimization based on semi-analytical techniques
191 -- 202Fulvio Corno, Uwe Gläser, Paolo Prinetto, Matteo Sonza Reorda, Heinrich Theodor Vierhaus, Massimo Violante. SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information
203 -- 211Yuejian Wu, Saman Adham. Scan-based BIST fault diagnosis
212 -- 219Atul Garg, Y. L. Le Coz, Hans J. Greub, R. B. Iverson, Robert F. Philhower, Pete M. Campbell, Cliff A. Maier, Sam A. Steidl, Matthew W. Ernest, Russell P. Kraft, Steven R. Carlough, J. W. Perry, Thomas W. Krawczyk Jr., John F. McDonald. Accurate high-speed performance prediction for full differential current-mode logic: the effect of dielectric anisotropy
219 -- 230Dimitrios Kagaris, Spyros Tragoudas. On the design of optimal counter-based schemes for test set embedding
231 -- 238How-Rern Lin, TingTing Hwang. On determining sensitization criterion in an iterative gate sizing process
238 -- 247Dhiraj K. Pradhan, Mitrajit Chatterjee. GLFSR-a new test pattern generator for built-in-self-test
248 -- 251Armen H. Zemanian, Victor A. Chang. Exterior templates for capacitance computations [interconnections]