| 15 | -- | 22 | Yih-Chih Chou, Youn-Long Lin. Effective enforcement of path-delay constraints inperformance-driven placement |
| 23 | -- | 31 | Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje. An analysis of the wire-load model uncertainty problem |
| 32 | -- | 41 | Jinan Lou, Shashidhar Thakur, Shankar Krishnamoorthy, Henry S. Sheng. Estimating routing congestion using probabilistic analysis |
| 42 | -- | 49 | Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani. Consistent floorplanning with hierarchical superconstraints |
| 50 | -- | 62 | Ankireddy Nalamalpu, Sriram Srinivasan, Wayne P. Burleson. Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters |
| 63 | -- | 71 | Ruiqi Tian, Xiaoping Tang, Martin D. F. Wong. Dummy-feature placement for chemical-mechanical polishinguniformity in a shallow-trench isolation process |
| 72 | -- | 80 | Xiaojian Yang, Ryan Kastner, Majid Sarrafzadeh. Congestion estimation during top-down placement |
| 81 | -- | 92 | Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh. Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning |
| 93 | -- | 101 | Sabyasachi Das, Sunil P. Khatri. An efficient and regular routing methodology for datapath designsusing net regularity extraction |