External Links

    Journal: IEEE Trans. on CAD of Integrated Circuits and Systems

    Volume 21, Issue 9

    998 -- 1010Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria. An instruction-level energy model for embedded VLIW architectures
    1011 -- 1024Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen. Symbolic modeling of periodically time-varying systems usingharmonic transfer matrices
    1025 -- 1036Jiang Hu, Sachin S. Sapatnekar. A timing-constrained simultaneous global routing algorithm
    1037 -- 1050Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha. High-level energy macromodeling of embedded software
    1051 -- 1067Eui-Young Chung, Luca Benini, Giovanni De Micheli, Gabriele Luculli, Marco Carilli. Value-sensitive automatic code specialization for embedded software
    1068 -- 1076Irith Pomeranz. On the use of random limited-scan to improve at-speed randompattern testing of scan circuits
    1077 -- 1087Kaijie Wu, Ramesh Karri. Algorithm level recomputing using allocation diversity: a registertransfer level approach to time redundancy-based concurrent errordetection
    1088 -- 1094Vikram Iyengar, Krishnendu Chakrabarty. System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints
    1095 -- 1101Dimitrios Kagaris, Spyros Tragoudas. On the nonenumerative path delay fault simulation problem
    1101 -- 1104Mutsumi Kimura, Satoshi Inoue, Tatsuya Shimoda. Table look-up model of thin-film transistors for circuit simulationusing spline interpolation with transformation by y=x+log(x)
    1105 -- 1113Dong Xiang, Hideo Fujiwara. Handling the pin overhead problem of DFTs for high-quality and at-speed tests

    Volume 21, Issue 8

    877 -- 888Ramesh Karri, Balakrishnan Iyer, Israel Koren. Phantom redundancy: a register transfer level technique for gracefully degradable data path synthesis
    889 -- 903Viktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana. Application-specific clustered VLIW datapaths: early exploration on a parameterized design space
    904 -- 915Kaustav Banerjee, Amit Mehrotra. Analysis of on-chip inductance effects for distributed RLC interconnects
    916 -- 927Steven C. Chan, Kenneth L. Shepard, Dae-Jin Kim. Static noise analysis for digital integrated circuits in partially depleted silicon-on-insulator technology
    928 -- 940Michael D. Hutton, Jonathan Rose, Derek G. Corneil. Automatic generation of synthetic sequential benchmark circuits
    941 -- 953Michele Favalli, Marcello Dalpasso. Bridging fault modeling and simulation for deep submicron CMOS ICs
    954 -- 968Seongmoon Wang, Sandeep K. Gupta. An automatic test pattern generator for minimizing switching activity during scan testing activity
    969 -- 974Alexandre César Muniz de Oliveira, Luiz Antonio Nogueira Lorena. A constructive genetic algorithm for gate matrix layout problems
    974 -- 979William N. N. Hung, Xiaoyu Song, El Mostapha Aboulhamid, Michael A. Driscoll. BDD minimization by scatter search
    980 -- 986Irith Pomeranz, Sudhakar M. Reddy. n-pass n-detection fault simulation and its applications
    987 -- 995Tianhao Zhang, Krishnendu Chakrabarty, Richard B. Fair. Design of reconfigurable composite microsystems based on hardware/software codesign principles

    Volume 21, Issue 7

    749 -- 762Cesare Alippi. A probably approximately correct framework to estimate performancedegradation in embedded systems
    763 -- 776Taku Uchino, Jason Cong. An interconnect energy model considering coupling effects
    777 -- 790Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh. Pattern routing: use and theory for increasing predictability andavoiding coupling
    791 -- 798Elena Gnani, Vincenzo Giudicissi, Radu Vissarion, Claudio Contiero, Massimo Rudan. Automatic 2-D and 3-D simulation of parasitic structures insmart-power integrated circuits
    810 -- 826Priyank Kalla, Maciej J. Ciesielski. A comprehensive approach to the partial scan problem using implicitstate enumeration
    827 -- 841Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha. High-level test compaction techniques
    842 -- 851Seongmoon Wang, Sandeep K. Gupta. DS-LFSR: a BIST TPG for low switching activity
    852 -- 859Dimitrios Kagaris. Linear dependencies in extended LFSMs
    859 -- 866Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas. A new built-in TPG method for circuits with random patternresistant faults
    866 -- 876Congguang Yang, Maciej J. Ciesielski. BDS: a BDD-based logic optimization system

    Volume 21, Issue 6

    645 -- 661Geert Van der Plas, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen. A layout synthesis methodology for array-type analog blocks
    662 -- 673Fei Yuan, Ajoy Opal. An efficient transient analysis algorithm for mildly nonlinearcircuits
    674 -- 684Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar. A new FPGA detailed routing approach via search-based Booleansatisfiability
    685 -- 693Min Ouyang, Michel Toulouse, Krishnaiyan Thulasiraman, Fred Glover, Jitender S. Deogun. Multilevel cooperative search for the circuit/hypergraphpartitioning problem
    694 -- 705Wanli Jiang, Bapiraju Vinnakota. Statistical threshold formulation for dynamic I::dd:: test
    706 -- 714Irith Pomeranz, Sudhakar M. Reddy. Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences
    715 -- 722Anshuman Chandra, Krishnendu Chakrabarty. Test data compression and decompression based on internal scanchains and Golomb coding
    723 -- 730Yungseon Eo, Jongin Shim, William R. Eisenstadt. A traveling-wave-based waveform approximation technique for thetiming verification of single transmission lines
    731 -- 738Antoni Ferré, Joan Figueras. Leakage power bounds in CMOS digital technologies
    739 -- 745Y. Shin, T. Sakurai. Power distribution analysis of VLSI interconnects using model orderreduction

    Volume 21, Issue 5

    505 -- 516Vasco M. Manquinho, João P. Marques Silva. Search pruning techniques in SAT-based branch-and-bound algorithmsfor the binate covering problem
    517 -- 533Baidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi. Efficient synthesis of OTA network for linear analog functions
    534 -- 543Wim Schoenmaker, Peter Meuris. Electromagnetic interconnects and passives modeling: softwareimplementation issues
    544 -- 553Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu. Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits
    554 -- 567Amir H. Salek, Jinan Lou, Massoud Pedram. Hierarchical buffered routing tree generation
    568 -- 581Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi. Fast and exact transistor sizing based on iterative relaxation
    582 -- 596Reinaldo A. Bergamaschi. Bridging the domains of high-level and logic synthesis
    597 -- 604Anshuman Chandra, Krishnendu Chakrabarty. Low-power scan testing and test data compression forsystem-on-a-chip
    605 -- 616Emrah Acar, Florentin Dartu, Lawrence T. Pileggi. TETA: transistor-level waveform evaluation for timing analysis
    617 -- 628Der-Cheng Huang, Wen-Ben Jone. A parallel transparent BIST method for embedded memory arrays bytolerating redundant operations
    628 -- 637Irith Pomeranz, Sudhakar M. Reddy. Property-based test generation for scan designs and the effects ofthe test application scheme and scan selection on the number ofdetectable faults

    Volume 21, Issue 4

    377 -- 394Paolo Crippa, Claudio Turchetti, Massimo Conti. A statistical methodology for the design of high-performance CMOScurrent-steering digital-to-analog converters
    395 -- 407Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen. Circuit simplification for the symbolic analysis of analogintegrated circuits
    408 -- 414Cheng-Ta Hsieh, Massoud Pedram. Architectural energy optimization by bus splitting
    415 -- 432Nestoras E. Evmorfopoulos, Georgios I. Stamoulis, John N. Avaritsiotis. A Monte Carlo approach for maximum power estimation based onextreme value theory
    433 -- 448José Luis Rosselló, Jaume Segura. Charge-based analytical model for the evaluation of powerconsumption in submicron CMOS buffers
    449 -- 465Der-Cheng Huang, Wen-Ben Jone. A parallel built-in self-diagnostic method for embedded memoryarrays
    466 -- 479Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou. On automatic-verification pattern generation for SoC withport-order fault model
    480 -- 490Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu. Fault simulation and test algorithm generation for random accessmemories
    491 -- 497Wai-Kei Mak. Min-cut partitioning with functional replication fortechnology-mapped circuits using minimum area overhead
    497 -- 497Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay. Correction to interconnect synthesis without wire tapering

    Volume 21, Issue 3

    253 -- 262Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh. Predicting potential performance for digital circuits
    263 -- 274Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky. Provably good global buffering by generalized multiterminalmulticommodity flow approximation
    275 -- 290Sung Tae Jung, Chris J. Myers. Direct synthesis of timed circuits from free-choice STGs
    291 -- 305Dinesh Ramanathan, Sandy Irani, Rajesh K. Gupta. An analysis of system level power management algorithms and theireffects on latency
    306 -- 318Qi Wang, Sarma B. K. Vrudhula. Algorithms for minimizing standby power in deep submicrometer, dual-V::t:: CMOS circuits
    319 -- 329Jason Cong, David Zhigang Pan. Wire width planning for interconnect performance optimization
    330 -- 336Weiping Shi, Jianguo Liu, Naveen Kakani, Tiejun Yu. A fast hierarchical algorithm for three-dimensional capacitanceextraction
    337 -- 348Akio Ushida, Yoshihiro Yamagami, Yoshifumi Nishio, Ikkei Kinouchi, Yasuaki Inoue. An efficient algorithm for finding multiple DC solutions based onthe SPICE-oriented Newton homotopy method
    349 -- 361Pramodchandran N. Variyam, Sasikumar Cherubal, Abhijit Chatterjee. Prediction of analog performance parameters using fast transienttesting
    362 -- 368Hiroshi Takahashi, Kwame Osei Boateng, Kewal K. Saluja, Yuzo Takamatsu. On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits

    Volume 21, Issue 2

    109 -- 130Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Alex Kondratyev, Luciano Lavagno, Ken S. Stevens, Alexander Taubin, Alexandre Yakovlev. Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions
    131 -- 144Yehea I. Ismail, Eby G. Friedman. DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect
    145 -- 158Zhaoyun Xing, Russell Kao. Shortest path search using tiles and piecewise linear costpropagation
    159 -- 168Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw. Hierarchical analysis of power distribution networks
    169 -- 183Stephen A. Edwards. An Esterel compiler for large control-dominated systems
    184 -- 203Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman. Retiming and clock scheduling for digital circuit optimization
    204 -- 216Khurram Muhammad, Kaushik Roy. A graph theoretic approach for synthesizing very low-complexityhigh-speed digital filters
    217 -- 231Said Hamdioui, A. J. van de Goor. Thorough testing of any multiport memory with linear tests
    232 -- 240Ki-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang. Domino logic synthesis based on implication graph
    240 -- 247Patrick H. Madden. Reporting of standard cell placement results

    Volume 21, Issue 12

    1377 -- 1394Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, Malay K. Ganai. Robust Boolean reasoning for equivalence checking and functional property verification
    1395 -- 1415Cagdas Akturan, Margarida F. Jacome. RS-FDRA: A register-sensitive software pipelining algorithm for embedded VLIW processors
    1416 -- 1424Tzyy-Kuen Tien, Shih-Chieh Chang, Tong-Kai Tsai. Crosstalk alleviation for dynamic PLAs
    1425 -- 1433Wim Schoenmaker, Wim Magnus, Peter Meuris, Bert Maleszka. Renormalization group meshes and the discretization of TCAD equations
    1434 -- 1445Ting-Yuan Wang, Charlie Chung-Ping Chen. 3-D Thermal-ADI: a linear-time chip level transient thermal simulator
    1446 -- 1458Emil Gizdarski, Hideo Fujiwara. SPIRIT: a highly robust combinational test generation algorithm
    1459 -- 1468Piotr R. Sidorowicz, Janusz A. Brzozowski. A framework for testing special-purpose memories
    1469 -- 1479Andreas G. Veneris, Magdy S. Abadir. Design rewiring using ATPG
    1480 -- 1488Maciej J. Ciesielski, Serkan Askar, Samuel Levitin. Analytical approach to layout generation of datapath cells
    1489 -- 1497Yungseon Eo, Seongkyun Shin, William R. Eisenstadt, Jongin Shim. Generalized traveling-wave-based waveform approximation technique for the efficient signal integrity verification of multicoupled transmission line system
    1497 -- 1502Xiaofang Gao, Juin J. Liou, Joe Bernier, Gregg Croft, Adelmo Ortiz-Conde. Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications
    1502 -- 1508Keerthi Heragu, Manish Sharma, Rahul Kundu, Ronald D. Blanton. Test vector generation for charge sharing failures in dynamic logic
    1509 -- 1517Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim. Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers
    1517 -- 1525Sandeep Koranne. Formulating SoC test scheduling as a network transportation problem
    1525 -- 1529In-Cheol Park, Hyeong-Ju Kang. Digital filter synthesis based on an algorithm to generate all minimal signed digit representations
    1530 -- 1539Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaudhuri. Design of hierarchical cellular automata for on-chip test pattern generator

    Volume 21, Issue 11

    1237 -- 1252Thanwa Sripramong, Christofer Toumazou. The invention of CMOS amplifiers using genetic programming and current-flow analysis
    1253 -- 1268Murali Kudlugi, Russell Tessier. Static scheduling of multidomain circuits for fast functional verification
    1269 -- 1283Hans M. Jacobson, Chris J. Myers. Efficient algorithms for exact two-level hazard-free logic minimization
    1284 -- 1305Yung-Hsiang Lu, Luca Benini, Giovanni De Micheli. Dynamic frequency scaling with buffer insertion for mixed workloads
    1306 -- 1316Carlo Brandolese, Fabio Salice, William Fornaciari, Donatella Sciuto. Static power modeling of 32-bit microprocessors
    1317 -- 1327Tony Givargis, Frank Vahid. Platune: a tuning framework for system-on-a-chip platforms
    1328 -- 1336Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu. Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories
    1337 -- 1343Ian G. Harris, Russell Tessier. Testing and diagnosis of interconnect faults in cluster-based FPGA architectures
    1343 -- 1352Yu-Min Lee, Charlie Chung-Ping Chen. Power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit method
    1352 -- 1363Philippe Maurine, Mustapha Rezzoug, Nadine Azémard, Daniel Auvergne. Transition time modeling in deep submicron CMOS
    1363 -- 1368Gang Qu. Publicly detectable watermarking for intellectual property authentication in VLSI design
    1368 -- 1372Mehmet Can Yildiz, Patrick H. Madden. Preferred direction Steiner trees

    Volume 21, Issue 10

    1117 -- 1131Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer. Analytical models for crosstalk excitation and propagation in VLSI circuits
    1132 -- 1147Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky. Area fill synthesis for uniform layout density
    1148 -- 1160Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm. A multigrid-like technique for power grid analysis
    1161 -- 1170Carl De Ranter, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen. CYCLONE: automated design and layout of RF LC-oscillators
    1171 -- 1179Bhargab B. Bhattacharya, Alexej Dmitriev, Michael Gössel, Krishnendu Chakrabarty. Synthesis of single-output space compactors for scan-based sequential circuits
    1180 -- 1195David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran. Slope propagation in static timing analysis
    1196 -- 1204Gregory Wolfe, Jennifer L. Wong, Miodrag Potkonjak. Watermarking graph partitioning solutions
    1205 -- 1209Minghorng Lai, Martin D. F. Wong. Maze routing with buffer insertion and wiresizing
    1209 -- 1211Rung-Bin Lin. Comments on Filling algorithms and analyses for layout density control
    1211 -- 1217Srivaths Ravi, Niraj K. Jha. Test synthesis of systems-on-a-chip
    1217 -- 1225Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici. Power profile manipulation: a new approach for reducing test application time under power constraints
    1225 -- 1232Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou. An automorphic approach to verification pattern generation for SoC design verification using port-order fault model

    Volume 21, Issue 1

    15 -- 22Yih-Chih Chou, Youn-Long Lin. Effective enforcement of path-delay constraints inperformance-driven placement
    23 -- 31Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje. An analysis of the wire-load model uncertainty problem
    32 -- 41Jinan Lou, Shashidhar Thakur, Shankar Krishnamoorthy, Henry S. Sheng. Estimating routing congestion using probabilistic analysis
    42 -- 49Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani. Consistent floorplanning with hierarchical superconstraints
    50 -- 62Ankireddy Nalamalpu, Sriram Srinivasan, Wayne P. Burleson. Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters
    63 -- 71Ruiqi Tian, Xiaoping Tang, Martin D. F. Wong. Dummy-feature placement for chemical-mechanical polishinguniformity in a shallow-trench isolation process
    72 -- 80Xiaojian Yang, Ryan Kastner, Majid Sarrafzadeh. Congestion estimation during top-down placement
    81 -- 92Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh. Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning
    93 -- 101Sabyasachi Das, Sunil P. Khatri. An efficient and regular routing methodology for datapath designsusing net regularity extraction
    runs on