| 109 | -- | 130 | Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Alex Kondratyev, Luciano Lavagno, Ken S. Stevens, Alexander Taubin, Alexandre Yakovlev. Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions |
| 131 | -- | 144 | Yehea I. Ismail, Eby G. Friedman. DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect |
| 145 | -- | 158 | Zhaoyun Xing, Russell Kao. Shortest path search using tiles and piecewise linear costpropagation |
| 159 | -- | 168 | Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw. Hierarchical analysis of power distribution networks |
| 169 | -- | 183 | Stephen A. Edwards. An Esterel compiler for large control-dominated systems |
| 184 | -- | 203 | Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman. Retiming and clock scheduling for digital circuit optimization |
| 204 | -- | 216 | Khurram Muhammad, Kaushik Roy. A graph theoretic approach for synthesizing very low-complexityhigh-speed digital filters |
| 217 | -- | 231 | Said Hamdioui, A. J. van de Goor. Thorough testing of any multiport memory with linear tests |
| 232 | -- | 240 | Ki-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang. Domino logic synthesis based on implication graph |
| 240 | -- | 247 | Patrick H. Madden. Reporting of standard cell placement results |