Journal: IEEE Trans. on CAD of Integrated Circuits and Systems

Volume 21, Issue 12

1377 -- 1394Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, Malay K. Ganai. Robust Boolean reasoning for equivalence checking and functional property verification
1395 -- 1415Cagdas Akturan, Margarida F. Jacome. RS-FDRA: A register-sensitive software pipelining algorithm for embedded VLIW processors
1416 -- 1424Tzyy-Kuen Tien, Shih-Chieh Chang, Tong-Kai Tsai. Crosstalk alleviation for dynamic PLAs
1425 -- 1433Wim Schoenmaker, Wim Magnus, Peter Meuris, Bert Maleszka. Renormalization group meshes and the discretization of TCAD equations
1434 -- 1445Ting-Yuan Wang, Charlie Chung-Ping Chen. 3-D Thermal-ADI: a linear-time chip level transient thermal simulator
1446 -- 1458Emil Gizdarski, Hideo Fujiwara. SPIRIT: a highly robust combinational test generation algorithm
1459 -- 1468Piotr R. Sidorowicz, Janusz A. Brzozowski. A framework for testing special-purpose memories
1469 -- 1479Andreas G. Veneris, Magdy S. Abadir. Design rewiring using ATPG
1480 -- 1488Maciej J. Ciesielski, Serkan Askar, Samuel Levitin. Analytical approach to layout generation of datapath cells
1489 -- 1497Yungseon Eo, Seongkyun Shin, William R. Eisenstadt, Jongin Shim. Generalized traveling-wave-based waveform approximation technique for the efficient signal integrity verification of multicoupled transmission line system
1497 -- 1502Xiaofang Gao, Juin J. Liou, Joe Bernier, Gregg Croft, Adelmo Ortiz-Conde. Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications
1502 -- 1508Keerthi Heragu, Manish Sharma, Rahul Kundu, Ronald D. Blanton. Test vector generation for charge sharing failures in dynamic logic
1509 -- 1517Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim. Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers
1517 -- 1525Sandeep Koranne. Formulating SoC test scheduling as a network transportation problem
1525 -- 1529In-Cheol Park, Hyeong-Ju Kang. Digital filter synthesis based on an algorithm to generate all minimal signed digit representations
1530 -- 1539Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaudhuri. Design of hierarchical cellular automata for on-chip test pattern generator