| 377 | -- | 394 | Paolo Crippa, Claudio Turchetti, Massimo Conti. A statistical methodology for the design of high-performance CMOScurrent-steering digital-to-analog converters |
| 395 | -- | 407 | Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen. Circuit simplification for the symbolic analysis of analogintegrated circuits |
| 408 | -- | 414 | Cheng-Ta Hsieh, Massoud Pedram. Architectural energy optimization by bus splitting |
| 415 | -- | 432 | Nestoras E. Evmorfopoulos, Georgios I. Stamoulis, John N. Avaritsiotis. A Monte Carlo approach for maximum power estimation based onextreme value theory |
| 433 | -- | 448 | José Luis Rosselló, Jaume Segura. Charge-based analytical model for the evaluation of powerconsumption in submicron CMOS buffers |
| 449 | -- | 465 | Der-Cheng Huang, Wen-Ben Jone. A parallel built-in self-diagnostic method for embedded memoryarrays |
| 466 | -- | 479 | Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou. On automatic-verification pattern generation for SoC withport-order fault model |
| 480 | -- | 490 | Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu. Fault simulation and test algorithm generation for random accessmemories |
| 491 | -- | 497 | Wai-Kei Mak. Min-cut partitioning with functional replication fortechnology-mapped circuits using minimum area overhead |
| 497 | -- | 497 | Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay. Correction to interconnect synthesis without wire tapering |