| 645 | -- | 661 | Geert Van der Plas, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen. A layout synthesis methodology for array-type analog blocks |
| 662 | -- | 673 | Fei Yuan, Ajoy Opal. An efficient transient analysis algorithm for mildly nonlinearcircuits |
| 674 | -- | 684 | Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar. A new FPGA detailed routing approach via search-based Booleansatisfiability |
| 685 | -- | 693 | Min Ouyang, Michel Toulouse, Krishnaiyan Thulasiraman, Fred Glover, Jitender S. Deogun. Multilevel cooperative search for the circuit/hypergraphpartitioning problem |
| 694 | -- | 705 | Wanli Jiang, Bapiraju Vinnakota. Statistical threshold formulation for dynamic I::dd:: test |
| 706 | -- | 714 | Irith Pomeranz, Sudhakar M. Reddy. Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences |
| 715 | -- | 722 | Anshuman Chandra, Krishnendu Chakrabarty. Test data compression and decompression based on internal scanchains and Golomb coding |
| 723 | -- | 730 | Yungseon Eo, Jongin Shim, William R. Eisenstadt. A traveling-wave-based waveform approximation technique for thetiming verification of single transmission lines |
| 731 | -- | 738 | Antoni Ferré, Joan Figueras. Leakage power bounds in CMOS digital technologies |
| 739 | -- | 745 | Y. Shin, T. Sakurai. Power distribution analysis of VLSI interconnects using model orderreduction |