| 253 | -- | 262 | Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh. Predicting potential performance for digital circuits |
| 263 | -- | 274 | Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky. Provably good global buffering by generalized multiterminalmulticommodity flow approximation |
| 275 | -- | 290 | Sung Tae Jung, Chris J. Myers. Direct synthesis of timed circuits from free-choice STGs |
| 291 | -- | 305 | Dinesh Ramanathan, Sandy Irani, Rajesh K. Gupta. An analysis of system level power management algorithms and theireffects on latency |
| 306 | -- | 318 | Qi Wang, Sarma B. K. Vrudhula. Algorithms for minimizing standby power in deep submicrometer, dual-V::t:: CMOS circuits |
| 319 | -- | 329 | Jason Cong, David Zhigang Pan. Wire width planning for interconnect performance optimization |
| 330 | -- | 336 | Weiping Shi, Jianguo Liu, Naveen Kakani, Tiejun Yu. A fast hierarchical algorithm for three-dimensional capacitanceextraction |
| 337 | -- | 348 | Akio Ushida, Yoshihiro Yamagami, Yoshifumi Nishio, Ikkei Kinouchi, Yasuaki Inoue. An efficient algorithm for finding multiple DC solutions based onthe SPICE-oriented Newton homotopy method |
| 349 | -- | 361 | Pramodchandran N. Variyam, Sasikumar Cherubal, Abhijit Chatterjee. Prediction of analog performance parameters using fast transienttesting |
| 362 | -- | 368 | Hiroshi Takahashi, Kwame Osei Boateng, Kewal K. Saluja, Yuzo Takamatsu. On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits |