| 1117 | -- | 1131 | Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer. Analytical models for crosstalk excitation and propagation in VLSI circuits |
| 1132 | -- | 1147 | Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky. Area fill synthesis for uniform layout density |
| 1148 | -- | 1160 | Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm. A multigrid-like technique for power grid analysis |
| 1161 | -- | 1170 | Carl De Ranter, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen. CYCLONE: automated design and layout of RF LC-oscillators |
| 1171 | -- | 1179 | Bhargab B. Bhattacharya, Alexej Dmitriev, Michael Gössel, Krishnendu Chakrabarty. Synthesis of single-output space compactors for scan-based sequential circuits |
| 1180 | -- | 1195 | David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran. Slope propagation in static timing analysis |
| 1196 | -- | 1204 | Gregory Wolfe, Jennifer L. Wong, Miodrag Potkonjak. Watermarking graph partitioning solutions |
| 1205 | -- | 1209 | Minghorng Lai, Martin D. F. Wong. Maze routing with buffer insertion and wiresizing |
| 1209 | -- | 1211 | Rung-Bin Lin. Comments on Filling algorithms and analyses for layout density control |
| 1211 | -- | 1217 | Srivaths Ravi, Niraj K. Jha. Test synthesis of systems-on-a-chip |
| 1217 | -- | 1225 | Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici. Power profile manipulation: a new approach for reducing test application time under power constraints |
| 1225 | -- | 1232 | Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou. An automorphic approach to verification pattern generation for SoC design verification using port-order fault model |