| 998 | -- | 1010 | Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria. An instruction-level energy model for embedded VLIW architectures |
| 1011 | -- | 1024 | Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen. Symbolic modeling of periodically time-varying systems usingharmonic transfer matrices |
| 1025 | -- | 1036 | Jiang Hu, Sachin S. Sapatnekar. A timing-constrained simultaneous global routing algorithm |
| 1037 | -- | 1050 | Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha. High-level energy macromodeling of embedded software |
| 1051 | -- | 1067 | Eui-Young Chung, Luca Benini, Giovanni De Micheli, Gabriele Luculli, Marco Carilli. Value-sensitive automatic code specialization for embedded software |
| 1068 | -- | 1076 | Irith Pomeranz. On the use of random limited-scan to improve at-speed randompattern testing of scan circuits |
| 1077 | -- | 1087 | Kaijie Wu, Ramesh Karri. Algorithm level recomputing using allocation diversity: a registertransfer level approach to time redundancy-based concurrent errordetection |
| 1088 | -- | 1094 | Vikram Iyengar, Krishnendu Chakrabarty. System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints |
| 1095 | -- | 1101 | Dimitrios Kagaris, Spyros Tragoudas. On the nonenumerative path delay fault simulation problem |
| 1101 | -- | 1104 | Mutsumi Kimura, Satoshi Inoue, Tatsuya Shimoda. Table look-up model of thin-film transistors for circuit simulationusing spline interpolation with transformation by y=x+log(x) |
| 1105 | -- | 1113 | Dong Xiang, Hideo Fujiwara. Handling the pin overhead problem of DFTs for high-quality and at-speed tests |