| 749 | -- | 762 | Cesare Alippi. A probably approximately correct framework to estimate performancedegradation in embedded systems |
| 763 | -- | 776 | Taku Uchino, Jason Cong. An interconnect energy model considering coupling effects |
| 777 | -- | 790 | Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh. Pattern routing: use and theory for increasing predictability andavoiding coupling |
| 791 | -- | 798 | Elena Gnani, Vincenzo Giudicissi, Radu Vissarion, Claudio Contiero, Massimo Rudan. Automatic 2-D and 3-D simulation of parasitic structures insmart-power integrated circuits |
| 810 | -- | 826 | Priyank Kalla, Maciej J. Ciesielski. A comprehensive approach to the partial scan problem using implicitstate enumeration |
| 827 | -- | 841 | Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha. High-level test compaction techniques |
| 842 | -- | 851 | Seongmoon Wang, Sandeep K. Gupta. DS-LFSR: a BIST TPG for low switching activity |
| 852 | -- | 859 | Dimitrios Kagaris. Linear dependencies in extended LFSMs |
| 859 | -- | 866 | Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas. A new built-in TPG method for circuits with random patternresistant faults |
| 866 | -- | 876 | Congguang Yang, Maciej J. Ciesielski. BDS: a BDD-based logic optimization system |