| 117 | -- | 122 | Claudio Turchetti, Guido Masetti. A CAD-Oriented Analytical MOSFET Model for High-Accuracy Applications |
| 123 | -- | 126 | Sharad C. Seth, Vishwani D. Agrawal. Characterizing the LSI Yield Equation from Wafer Test Data |
| 126 | -- | 134 | Thomas A. Johnson, Ronald W. Knepper, Victor Marcello, Wen Wang. Chip Substrate Resistance Modeling Technique for Integrated Circuit Design |
| 135 | -- | 141 | E. Barke. A Network Comparison Algorithm for Layout Verification of Integrated Circuits |
| 142 | -- | 149 | Fabio Somenzi, Silvano Gai, Marco Mezzalama, Paolo Prinetto. PART: Programmable Array Testing Based on a Partitioning Algorithm |
| 150 | -- | 155 | David J. Lu, Edward J. McCluskey. Quantitative Evaluation of Self-Checking Circuits |
| 156 | -- | 163 | Yun Kang Chen, Mei Lun Liu. Three-Layer Channel Routing |