| 165 | -- | 171 | V. Visvanathan, Alberto L. Sangiovanni-Vincentelli. A Computational Approach for the Diagnosability of Dynamical Circuits |
| 172 | -- | 177 | Takeshi Tokuda, Jiro Korematsu, Osamu Tomisawa, S. Asai, I. Ohkura, T. Enomoto. A Hierarchical Standard Cell Approach for Custom VLSI Design |
| 178 | -- | 183 | Tom Tsan-Kuo Tarng, Malgorzata Marek-Sadowska, Ernest S. Kuh. An Efficient Single-Row Routing Algorithm |
| 184 | -- | 190 | Malgorzata Marek-Sadowska. An Unconstrained Topological Via Minimization Problem for Two-Layer Routing |
| 191 | -- | 199 | J. R. Egan, C. L. Liu. Bipartite Folding and Partitioning of a PLA |
| 200 | -- | 208 | John P. Hayes. Fault Modeling for Digital MOS Integrated Circuits |
| 208 | -- | 217 | F. J. Hill, Zainalabedin Navabi, C. H. Chiang, Duan-Ping Chen, M. Masud. Hardware Compilation from an RTL to a Storage Logic Array Target |
| 218 | -- | 225 | Chung-Kuan Cheng, Ernest S. Kuh. Module Placement Based on Resistive Network Optimization |
| 226 | -- | 234 | Ronald A. Rohrer, Hassan Nosrati, Kenneth W. Heizer. Quasi-Static Control of Explicit Algorithms for Transient Analysis |
| 235 | -- | 241 | Sangyong Han, Sartaj Sahni. Single-Row Routing in Narrow Streets |
| 242 | -- | 249 | John K. Ousterhout. The User Interface and Implementation of an IC Layout Editor |
| 250 | -- | 255 | H. N. Brady. An Approach to Topological Pin Assignment |
| 256 | -- | 256 | Giovanni De Micheli, Alberto L. Sangiovanni-Vincentelli. Correction to Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications |