| 1577 | -- | 1590 | Kan Zhong, Duo Liu, Liang Liang, Xiao Zhu, Linbo Long, Yi Wang, Edwin Hsing-Mean Sha. Energy-Efficient In-Memory Paging for Smartphones |
| 1591 | -- | 1604 | Razvan Nane, Vlad Mihai Sima, Christian Pilato, Jongsok Choi, Blair Fort, Andrew Canis, Yu-Ting Chen, Hsuan Hsiao, Stephen Dean Brown, Fabrizio Ferrandi, Jason Helge Anderson, Koen Bertels. A Survey and Evaluation of FPGA High-Level Synthesis Tools |
| 1605 | -- | 1617 | Jiatao Ding, Jiajia Chen, Chip-Hong Chang. A New Paradigm of Common Subexpression Elimination by Unification of Addition and Subtraction |
| 1618 | -- | 1629 | Subhendu Roy, Derong Liu, Jagmohan Singh, Junhyung Um, David Z. Pan. OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions |
| 1630 | -- | 1639 | Ayman Yehia Hamouda, Mohab Anis, Karim S. Karim. Model-Based Initial Bias (MIB): Toward a Single-Iteration Optical Proximity Correction |
| 1640 | -- | 1652 | Majid Ahadi, Sourajeet Roy. Sparse Linear Regression (SPLINER) Approach for Efficient Multidimensional Uncertainty Quantification of High-Speed Circuits |
| 1653 | -- | 1666 | Konstantis Daloukas, Nestor E. Evmorfopoulos, Panagiota Tsompanopoulou, George I. Stamoulis. Parallel Fast Transform-Based Preconditioners for Large-Scale Power Grid Analysis on Graphics Processing Units (GPUs) |
| 1667 | -- | 1680 | Gadi Oxman, Shlomo Weiss. An NoC Simulator That Supports Deflection Routing, GPU/CPU Integration, and Co-Simulation |
| 1681 | -- | 1694 | Hao Zhuang, Wenjian Yu, Shih-Hung Weng, Ilgweon Kang, Jeng-Hau Lin, Xiang Zhang, Ryan Coutts, Chung-Kuan Cheng. Simulation Algorithms With Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks |
| 1695 | -- | 1706 | Denis Oyaro, Piero Triverio. TurboMOR-RC: An Efficient Model Order Reduction Technique for RC Networks With Many Ports |
| 1707 | -- | 1720 | Sandeep Kumar Samal, Shreepad Panth, Kambiz Samadi, Mehdi Saedi, Yang Du, Sung Kyu Lim. Adaptive Regression-Based Thermal Modeling and Optimization for Monolithic 3-D ICs |
| 1721 | -- | 1729 | Yuhan Zhou, Yong Zhang, Vivek Sarin, Wangqi Qiu, Weiping Shi. Macro Model of Advanced Devices for Parasitic Extraction |
| 1730 | -- | 1743 | Ya-Ting Shyu, Jai-Ming Lin, Che-Chun Lin, Chun-Po Huang, Soon-Jyh Chang. An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs |
| 1744 | -- | 1754 | Tao Wang, Chun Zhang, Jinjun Xiong, Pei-Wen Luo, Liang-Chia Cheng, Yiyu Shi. On the Optimal Threshold Voltage Computation of On-Chip Noise Sensors |
| 1755 | -- | 1762 | Irith Pomeranz. Static Test Compaction for Functional Test Sequences With Restoration of Functional Switching Activity |
| 1763 | -- | 1767 | Wooheon Kang, Changwook Lee, Hyunyul Lim, Sungho Kang. A New 3-D Fuse Architecture to Improve Yield of 3-D Memories |