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    Journal: IEEE Trans. on CAD of Integrated Circuits and Systems

    Volume 35, Issue 9

    1397 -- 1410Florin Burcea, Husni M. Habal, Helmut E. Graeb. A New Chessboard Placement and Sizing Method for Capacitors in a Charge-Scaling DAC by Worst-Case Analysis of Nonlinearity
    1411 -- 1424Muhammad Yasin, Jeyavijayan J. V. Rajendran, Ozgur Sinanoglu, Ramesh Karri. On Improving the Security of Logic Locking
    1425 -- 1434Ming-Chang Yang, Yuan-Hao Chang, Yuan-Hung Kuan, Che-Wei Tsao. Graceful Space Degradation: An Uneven Space Management for Flash Storage Devices
    1435 -- 1448Xiaoming Chen, Lin Wang, Boxun Li, Yu Wang, Xin Li, Yongpan Liu, Huazhong Yang. Modeling Random Telegraph Noise as a Randomness Source and its Application in True Random Number Generation
    1449 -- 1460Wei-Che Wang, Puneet Gupta. Efficient Layout Generation and Design Evaluation of Vertical Channel Devices
    1461 -- 1474Ping Chi, Wang-Chien Lee, Yuan Xie 0001. + -Tree for Emerging Nonvolatile Memory-Based Main Memory
    1475 -- 1488Shouyi Yin, Jiangyuan Gu, Dajiang Liu, Leibo Liu, Shaojun Wei. dd CGRAs
    1489 -- 1502Pietro Buccella, Camillo Stefanucci, Hao Zou, Yasser Moursy, Ramy Iskander, Jean-Michel Sallese, Maher Kayal. Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs
    1503 -- 1508Hadi Ahmadi Balef, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram. All-Region Statistical Model for Delay Variation Based on Log-Skew-Normal Distribution
    1509 -- 1518Javad Yavand Hasani. Three-Port Model of a Modern MOS Transistor in Millimeter Wave Band, Considering Distributed Effects
    1519 -- 1531Iou-Jen Liu, Shao-Yun Fang, Yao-Wen Chang. Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process
    1532 -- 1545Yunfeng Yang, Wai-Shing Luk, David Z. Pan, Hai Zhou, Changhao Yan, Dian Zhou, Xuan Zeng. Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography
    1546 -- 1556Abdulazim Amouri, Jochen Hepp, Mehdi Baradaran Tahoori. Built-In Self-Heating Thermal Testing of FPGAs
    1557 -- 1568Valeriy Balabanov, Shuo-Ren Lin, Jie-Hong R. Jiang. Flexibility and Optimization of QBF Skolem-Herbrand Certificates
    1569 -- 1573Gang Wu, Chris Chu. Detailed Placement Algorithm for VLSI Design With Double-Row Height Standard Cells

    Volume 35, Issue 8

    1229 -- 1242Mark Po-Hung Lin, Po-Hsun Chang, Shuenn-Yuh Lee, Helmut E. Graeb. DeMixGen: Deterministic Mixed-Signal Layout Generation With Separated Analog and Digital Signal Paths
    1243 -- 1254Hung-Chih Ou, Kai-Han Tseng, Jhao-Yan Liu, I-Peng Wu, Yao-Wen Chang. Layout-Dependent Effects-Aware Analytical Analog Placement
    1255 -- 1268Fa Wang, Paolo Cachecho, Wangyang Zhang, Shupeng Sun, Xin Li 0001, Rouwaida Kanj, Chenjie Gu. Bayesian Model Fusion: Large-Scale Performance Modeling of Analog and Mixed-Signal Circuits by Reusing Early-Stage Data
    1269 -- 1282Junlong Zhou, Tongquan Wei, Mingsong Chen, Jianming Yan, Xiaobo Sharon Hu, Yue Ma. Thermal-Aware Task Scheduling for Energy Minimization in Heterogeneous Real-Time MPSoC Systems
    1283 -- 1296Hailong Yao, Qin Wang, Yiren Shen, Tsung-Yi Ho, Yici Cai. Integrated Functional and Washing Routing Optimization for Cross-Contamination Removal in Digital Microfluidic Biochips
    1297 -- 1308Rui Jia, Hai-Gang Yang, Colin Yu Lin, Rui Chen, Xin Gang Wang, Zhenhong Guo. A Computationally Efficient Reconfigurable FIR Filter Architecture Based on Coefficient Occurrence Probability
    1309 -- 1317Marko Magerl, Vladimir Ceperic, Adrijan Baric. Echo State Networks for Black-Box Modeling of Integrated Circuits
    1318 -- 1331Ermao Cai, Da-Cheng Juan, Siddharth Garg, Jinpyo Park, Diana Marculescu. Learning-Based Power/Performance Optimization for Many-Core Systems With Extended-Range Voltage/Frequency Scaling
    1332 -- 1344Jin-Tai Yan. Efficient Layer Assignment of Bus-Oriented Nets in High-Speed PCB Designs
    1345 -- 1357Yu-Hsuan Su, Yu-Chen Huang, Liang-Chun Tsai, Yao-Wen Chang, Shayak Banerjee. Fast Lithographic Mask Optimization Considering Process Variation
    1358 -- 1371Anup Das 0001, Geoff V. Merrett, Mirco Tribastone, Bashir M. Al-Hashimi. Workload Change Point Detection for Runtime Thermal Management of Embedded Systems
    1372 -- 1385Yubiao Pan, Yongkun Li, Yinlong Xu, Biaobiao Shen. DCS: Diagonal Coding Scheme for Enhancing the Endurance of SSD-Based RAID Arrays
    1386 -- 1395Alvaro Gómez-Pau, Luz Balado, Joan Figueras. Efficient Production Binning Using Octree Tessellation in the Alternate Measurements Space

    Volume 35, Issue 7

    1053 -- 1066Sven Tenzing Choden Konigsmark, Deming Chen, Martin D. F. Wong. PolyPUF: Physically Secure Self-Divergence
    1067 -- 1078Abhishek Basak, Swarup Bhunia. P-Val: Antifuse-Based Package-Level Defense Against Counterfeit ICs
    1079 -- 1091Keonsoo Ha, JaeYong Jeong, Jihong Kim. An Integrated Approach for Managing Read Disturbs in High-Density NAND Flash Memory
    1092 -- 1104Hyeon Uk Sim, Hongsik Lee, Seongseok Seo, Jongeun Lee. Mapping Imperfect Loops to Coarse-Grained Reconfigurable Architectures
    1105 -- 1113Kuo-Hsuan Meng, Vrashank Shukla, Elyse Rosenbaum. Full-Component Modeling and Simulation of Charged Device Model ESD
    1114 -- 1124Wangkun Jia, Brian T. Helenbrook, Ming-C. Cheng. Fast Thermal Simulation of FinFET Circuits Based on a Multiblock Reduced-Order Model
    1125 -- 1129Lucian Vintan, Radu Chis, Muhammad Ali Ismail, Cristian Cotofana. Improving Computing Systems Automatic Multiobjective Optimization Through Meta-Optimization
    1130 -- 1137Hung-I. Lee, Chen-Yo Han, James Chien-Mo Li. A Multicircuit Simulator Based on Inverse Jacobian Matrix Reuse
    1138 -- 1150Li Yu, Sharad Saxena, Christopher Hess, Ibrahim Abe M. Elfadel, Dimitri A. Antoniadis, Duane S. Boning. Compact Model Parameter Extraction Using Bayesian Inference, Incomplete New Measurements, and Optimal Bias Selection
    1151 -- 1164Di Zhu, Siyu Yue, Naehyuck Chang, Massoud Pedram. Toward a Profitable Grid-Connected Hybrid Electrical Energy Storage System for Residential Use
    1165 -- 1178Yun Liang, Muhammad Teguh Satria, Kyle Rupnow, Deming Chen. An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization
    1179 -- 1191Kai Hu, Bhargab B. Bhattacharya, Krishnendu Chakrabarty. Fault Diagnosis for Leakage and Blockage Defects in Flow-Based Microfluidic Biochips
    1192 -- 1205Tianjian Li, Feng Xie, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty, Naifeng Jing, Li Jiang. A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs
    1206 -- 1218Tim Pruss, Priyank Kalla, Florian Enescu. Efficient Symbolic Computation for Word-Level Abstraction From Combinational Circuits for Verification Over Finite Fields
    1219 -- 1223Taewoo Han, Inhyuk Choi, Hyunggoy Oh, Sungho Kang. Parallelized Network-on-Chip-Reused Test Access Mechanism for Multiple Identical Cores
    1224 -- 1228Angelo Ciccazzo, Gianni Di Pillo, Vittorio Latorre. A SVM Surrogate Model-Based Method for Parametric Yield Optimization

    Volume 35, Issue 6

    877 -- 890Rishad A. Shafik, Sheng Yang, Anup Das 0001, Luis Alfonso Maeda-Nunez, Geoff V. Merrett, Bashir M. Al-Hashimi. Learning Transfer-Based Adaptive Energy Minimization in Embedded Systems
    891 -- 904Linbo Long, Duo Liu, Liang Liang, Xiao Zhu, Kan Zhong, Zili Shao, Edwin Hsing-Mean Sha. Morphable Resistive Memory Optimization for Mobile Virtualization
    905 -- 918Xue-Yang Zhu, Marc Geilen, Twan Basten, Sander Stuijk. Multiconstraint Static Scheduling of Synchronous Dataflow Graphs Via Retiming and Unfolding
    919 -- 930Hamid Savoj, Alan Mishchenko, Robert K. Brayton. m-Inductive Property of Sequential Circuits
    931 -- 942Stephan Weber, Tiago Ressurreicao, Candido Duarte. Yield Prediction With a New Generalized Process Capability Index Applicable to Non-Normal Data
    943 -- 956Srinivas Jallepalli, Ram Mooraka, Sanjay Parihar, Earl Hunter, Elie Maalouf. Employing Scaled Sigma Sampling for Efficient Estimation of Rare Event Probabilities in the Absence of Input Domain Mapping
    957 -- 970Srinivas Jallepalli, Ram Mooraka, Sanjay Parihar, Earl Hunter, Elie Maalouf. Rapid Assessment of Design Sensitivity to Process Excursions via Scaled Sigma Sampling
    971 -- 984Changhai Liao, Jun Tao, Xuan Zeng, Yangfeng Su, Dian Zhou, Xin Li 0001. Efficient Spatial Variation Modeling of Nanoscale Integrated Circuits Via Hidden Markov Tree
    985 -- 998Shi Jin, Fangming Ye, Zhaobo Zhang, Krishnendu Chakrabarty, Xinli Gu. Efficient Board-Level Functional Fault Diagnosis With Missing Syndromes
    999 -- 1011Yanhong Zhou, Tiancheng Wang, Huawei Li, Tao Lv, Xiaowei Li 0001. Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving
    1012 -- 1025Xiaobing Shi, Nicola Nicolici. On-Chip Cube-Based Constrained-Random Stimuli Generation for Post-Silicon Validation
    1026 -- 1039Alberto Griggio, Marco Roveri. Comparing Different Variants of the ic3 Algorithm for Hardware Model Checking
    1040 -- 1051Leibin Ni, Sai Manoj P. D., Yang Song, Chenjie Gu, Hao Yu. A Zonotoped Macromodeling for Eye-Diagram Verification of High-Speed I/O Links With Jitter and Parameter Variations

    Volume 35, Issue 5

    697 -- 698Shiyan Hu, Xiaobo Sharon Hu, Albert Y. Zomaya. Guest Editorial Leveraging Design Automation Techniques for Cyber-Physical System Design
    699 -- 711Bowen Zheng, Peng Deng, Anguluri Rajasekhar, Qi Zhu, Fabio Pasqualetti. Cross-Layer Codesign for Secure Cyber-Physical Systems
    712 -- 723Mianxiong Dong, Kaoru Ota, Laurence T. Yang, Anfeng Liu, Minyi Guo. LSCD: A Low-Storage Clone Detection Protocol for Cyber-Physical Systems
    724 -- 737Daming Zhang, Yongpan Liu, Jinyang Li, Chun Jason Xue, Xueqing Li, Yu Wang, Huazhong Yang. Solar Power Prediction Assisted Intra-task Scheduling for Nonvolatile Sensor Nodes
    738 -- 749Domenico Balsamo, Anup Das 0001, Alex S. Weddell, Davide Brunelli, Bashir M. Al-Hashimi, Geoff V. Merrett, Luca Benini. Graceful Performance Modulation for Power-Neutral Transient Computing Systems
    750 -- 763Hyung-Chan An, Hoeseok Yang, Soonhoi Ha. A Formal Approach to Power Optimization in CPSs With Delay-Workload Dependence Awareness
    764 -- 777Mirela Alistar, Paul Pop, Jan Madsen. Synthesis of Application-Specific Fault-Tolerant Digital Microfluidic Biochip Architectures
    778 -- 791Muhammad Umer Khan, Shuai Li, Qixin Wang, Zili Shao. CPS Oriented Control Design for Networked Surveillance Robots With Multiple Physical Constraints
    792 -- 805Bin Zhou, Wei Zhang, Thambipillai Srikanthan, Jason Teo Kian Jin, Vivek Chaturvedi, Tao Luo. Cost-efficient Acceleration of Hardware Trojan Detection Through Fan-Out Cone Analysis and Weighted Random Pattern Technique
    806 -- 819Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli. Majority-Inverter Graph: A New Paradigm for Logic Optimization
    820 -- 831Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan. Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs
    832 -- 843Qinggao Mei, Wim Schoenmaker, Shih-Hung Weng, Hao Zhuang, Chung-Kuan Cheng, Quan Chen. An Efficient Transient Electro-Thermal Simulation Framework for Power Integrated Circuits
    844 -- 857Anastasios Psarras, JungHee Lee, Ioannis Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos. PhaseNoC: Versatile Network Traffic Isolation Through TDM-Scheduled Virtual Channels
    858 -- 871Seyed Nematollah Adel Ahmadyan, Shobha Vasudevan. Automated Transient Input Stimuli Generation for Analog Circuits
    872 -- 0Emad Ebeid, Franco Fummi, Davide Quaglia. Erratum to "Model-Driven Design of Network Aspects of Distributed Embedded Systems"

    Volume 35, Issue 4

    521 -- 534Tony F. Wu, Karthik Ganesan, Yunqing Alexander Hu, H.-S. Philip Wong, S. Simon Wong, Subhasish Mitra. TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits
    535 -- 548Firew Siyoum, Marc Geilen, Henk Corporaal. End-to-End Latency Analysis of Dataflow Scenarios Mapped Onto Shared Heterogeneous Resources
    549 -- 558Soumitra Pal, Aminul Islam. Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications
    559 -- 572Kai Hu, Tsung-Yi Ho, Krishnendu Chakrabarty. Wash Optimization and Analysis for Cross-Contamination Removal Under Physical Constraints in Flow-Based Microfluidic Biochips
    573 -- 585Bajaj Ronak, Suhaib A. Fahmy. Mapping for Maximum Performance on FPGA DSP Blocks
    586 -- 597Hsuan-Ming Huang, Charles H.-P. Wen. Layout-Based Soft Error Rate Estimation Framework Considering Multiple Transient Faults - From Device to Circuit Level
    598 -- 610Hui-Ju Katherine Chiang, Chi-Yuan Liu, Jie-Hong R. Jiang, Yao-Wen Chang. Simultaneous EUV Flare Variation Minimization and CMP Control by Coupling-Aware Dummification
    611 -- 622Qing Xie, Donghwa Shin, Naehyuck Chang, Massoud Pedram. Joint Charge and Thermal Management for Batteries in Portable Systems With Hybrid Power Sources
    623 -- 636Francesco Beneventi, Andrea Bartolini, Pascal Vivet, Luca Benini. Thermal Analysis and Interpolation Techniques for a Logic + WideIO Stacked DRAM Test Chip
    637 -- 650Florian Sagstetter, Peter Waszecki, Sebastian Steinhorst, Martin Lukasiewycz, Samarjit Chakraborty. Multischedule Synthesis for Variant Management in Automotive Time-Triggered Systems
    651 -- 664Fazal Hameed, Lars Bauer, Jörg Henkel. Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency Reduction
    665 -- 678Fangming Ye, Farshad Firouzi, Yang Yang, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori. On-Chip Droop-Induced Circuit Delay Prediction Based on Support-Vector Machines
    679 -- 690Zheng Gong, Rashid Rashidzadeh. TSV Extracted Equivalent Circuit Model and an On-Chip Test Solution
    691 -- 694Min Huang, Zhaoqing Liu, Liyan Qiao, Yi Wang, Zili Shao. An Endurance-Aware Metadata Allocation Strategy for MLC NAND Flash Memory Storage Systems

    Volume 35, Issue 3

    345 -- 0Vijaykrishnan Narayanan, Charles J. Alpert, Sara Dailey. Editorial
    346 -- 356Prajit Nandi, Hirak Talukdar, Dhiraj Kumar, Ashvinkumar G. Katakwar. A Novel Approach to Design SAR-ADC: Design Partitioning Method
    357 -- 366Trey Reece, William H. Robinson. Detection of Hardware Trojans in Third-Party Intellectual Property Using Untrusted Modules
    367 -- 379Mojtaba Ebrahimi, Hossein Asadi, Rajendra Bishnoi, Mehdi Baradaran Tahoori. Layout-Based Modeling and Mitigation of Multiple Event Transients
    380 -- 393Jianlei Yang, Peiyuan Wang, Yaojun Zhang, Yuanqing Cheng, Weisheng Zhao, Yiran Chen, Hai Helen Li. Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach
    394 -- 406Benjamin Carrión Schäfer. Probabilistic Multiknob High-Level Synthesis Design Space Exploration Acceleration
    407 -- 418Jason Cong, Peng Li, Bingjun Xiao, Peng Zhang. An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers
    419 -- 432Alberto A. Del Barrio, Jason Cong, Román Hermida. A Distributed Clustered Architecture to Tackle Delay Variations in Datapath Synthesis
    433 -- 446Qi Guo, Tianshi Chen, Yunji Chen, Franz Franchetti. Accelerating Architectural Simulation Via Statistical Techniques: A Survey
    447 -- 457Fan Lan, Yun Pan, Kwang-Ting (Tim) Cheng. An Efficient Network-on-Chip Yield Estimation Approach Based on Gibbs Sampling
    458 -- 470Yu-Chung Hsiao, Luca Daniel. CAPLET: A Highly Parallelized Field Solver for Capacitance Extraction Using Instantiable Basis Functions
    471 -- 484Zhiliang Qian, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui, Diana Marculescu, Radu Marculescu. A Support Vector Regression (SVR)-Based Latency Model for Network-on-Chip (NoC) Architectures
    485 -- 498Xueyang Wang, Ramesh Karri. Reusing Hardware Performance Counters to Detect and Identify Kernel Control-Flow Modifying Rootkits
    499 -- 512Dong Xiang, Kele Shen, Bhargab B. Bhattacharya, Xiaoqing Wen, Xijiang Lin. Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill
    513 -- 517Caio Araujo T. Campos, Abner Luis Panho Marciano, Omar P. Vilela Neto, Frank Sill Torres. USE: A Universal, Scalable, and Efficient Clocking Scheme for QCA

    Volume 35, Issue 2

    173 -- 186Yiqun Wang, Yongpan Liu, Cong Wang, Zewei Li, Xiao Sheng, Hyung Gyu Lee, Naehyuck Chang, Huazhong Yang. Storage-Less and Converter-Less Photovoltaic Energy Harvesting With Maximum Power Point Tracking for Internet of Things
    187 -- 196Mohammad Javad Sharifi, Davoud Bahrepour. A Multiloop and Full Amplitude Hysteresis Model for Molecular Electronics
    197 -- 210André Lange, Christoph Sohrmann, Roland Jancke, Joachim Haase, Binjie Cheng, Asen Asenov, Ulf Schlichtmann. Multivariate Modeling of Variability Supporting Non-Gaussian and Correlated Parameters
    211 -- 219Anwar Jarndal, Riadh Essaadali, Ammar B. Kouki. A Reliable Model Parameter Extraction Method Applied to AlGaN/GaN HEMTs
    220 -- 231Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar. Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization
    232 -- 245Xuan Dong, Lihong Zhang. Lithography-Aware Analog Layout Retargeting
    246 -- 259Seong-I. Lei, Wai-Kei Mak. Optimizing Pin Assignment and Escape Routing for Blind-via-Based PCBs
    260 -- 273Junxiu Liu, Jim Harkin, Yuhua Li, Liam P. Maguire. Fault-Tolerant Networks-on-Chip Routing With Coarse and Fine-Grained Look-Ahead
    274 -- 284Sungyoul Seo, Yong Lee, Sungho Kang. Tri-State Coding Using Reconfiguration of Twisted Ring Counter for Test Data Compression
    285 -- 297Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li 0001, Sandip Kundu. Abstraction-Guided Simulation Using Markov Analysis for Functional Verification
    298 -- 308Joon-Sung Yang, Jinsuk Chung, Nur A. Touba. Enhancing Superset X-Canceling Method With Relaxed Constraints on Fault Observation
    309 -- 322Mukesh Agrawal, Krishnendu Chakrabarty, Bill Eklow. A Distributed, Reconfigurable, and Reusable BIST Infrastructure for Test and Diagnosis of 3-D-Stacked ICs
    323 -- 336Fangming Ye, Zhaobo Zhang, Krishnendu Chakrabarty, Xinli Gu. Adaptive Board-Level Functional Fault Diagnosis Using Incremental Decision Trees
    337 -- 341Irith Pomeranz. Balancing the Numbers of Detected Faults for Improved Test Set Quality

    Volume 35, Issue 12

    1956 -- 1967Haeseung Lee, Mohammad Abdullah Al Faruque. Run-Time Scheduling Framework for Event-Driven Applications on a GPU-Based Embedded System
    1968 -- 1980Domenico Balsamo, Alex S. Weddell, Anup Das 0001, Alberto Rodriguez Arreola, Davide Brunelli, Bashir M. Al-Hashimi, Geoff V. Merrett, Luca Benini. Hibernus++: A Self-Calibrating and Adaptive System for Transiently-Powered Embedded Devices
    1981 -- 1994Tsun-Ming Tseng, Bing Li, Mengchu Li, Tsung-Yi Ho, Ulf Schlichtmann. Reliability-Aware Synthesis With Dynamic Device Mapping and Fluid Routing for Flow-Based Microfluidic Biochips
    1995 -- 2007Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Giovanni De Micheli. Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation
    2008 -- 2017Shouzhen Gu, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Yiran Chen, Jingtong Hu. A Time, Energy, and Area Efficient Domain Wall Memory-Based SPM for Embedded Systems
    2018 -- 2031Vincenzo Rana, Ivan Beretta, Francesco Bruschi, Alessandro Antonio Nacci, David Atienza, Donatella Sciuto. Efficient Hardware Design of Iterative Stencil Loops
    2032 -- 2045Ying Chen, Tan Nguyen, Yao Chen, Swathi T. Gurumani, Yun Liang, Kyle Rupnow, Jason Cong, Wen-mei W. Hwu, Deming Chen. FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow
    2046 -- 2055Jea Woo Park, Robert Todd, Xiaoyu Song. Geometric Pattern Match Using Edge Driven Dissected Rectangles and Vector Space
    2056 -- 2067Taigon Song, Shreepad Panth, Yoo-Jin Chae, Sung Kyu Lim. More Power Reduction With 3-Tier Logic-on-Logic 3-D ICs
    2068 -- 2081Seyong Ahn, Minseok Kang, Marios C. Papaefthymiou, Taewhan Kim. Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling
    2082 -- 2092Qiushi Han, Ming Fan, Ou Bai, Shaolei Ren, Gang Quan. Temperature-Constrained Feasibility Analysis for Multicore Scheduling
    2093 -- 2103Baris Arslan, Alex Orailoglu. Aggressive Test Cost Reductions Through Continuous Test Effectiveness Assessment
    2104 -- 2117Stephan EggersgluB, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler. On Optimization-Based ATPG and Its Application for Highly Compacted Test Sets
    2118 -- 2130Pouya Taatizadeh, Nicola Nicolici. Automated Selection of Assertions for Bit-Flip Detection During Post-Silicon Validation
    2131 -- 2142Cunxi Yu, Walter Brown, Duo Liu, André Rossi, Maciej J. Ciesielski. Formal Verification of Arithmetic Circuits by Function Extraction
    2143 -- 2147Ke Huang, Jian Wen, Jim Willmore. Test-Suite-Based Analog/RF Test Time Reduction Using Canonical Correlation
    2148 -- 2152Changhai Liao, Jun Tao, Handi Yu, Zhangwen Tang, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li 0001. Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors

    Volume 35, Issue 11

    1769 -- 1782Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Partha Pratim Pande, Vincenzo Catania. On-Chip Communication Energy Reduction Through Reliability Aware Adaptive Voltage Swing Scaling
    1783 -- 1796Kostas Siozios, Dimitrios Soudris. A Customizable Framework for Application Implementation onto 3-D FPGAs
    1797 -- 1810Yi-Hsiang Lai, Chi-Chuan Chuang, Jie-Hong R. Jiang. Scalable Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits
    1811 -- 1824Hai-Bao Chen, Sheldon X.-D. Tan, Xin Huang, Taeyoung Kim, Valeriy Sukharev. Analytical Modeling and Characterization of Electromigration Effects for Multibranch Interconnect Trees
    1825 -- 1835A. Gokcen Mahmutoglu, Alper Demir. Non-Monte Carlo Analysis of Low-Frequency Noise: Exposition of Intricate Nonstationary Behavior and Comparison With Legacy Models
    1836 -- 1847Ya Wang, Peng Li, Suming Lai. Robust and Efficient Transistor-Level Envelope-Following Analysis of PWM/PFM/PSM DC-DC Converters
    1848 -- 1861Xin Huang, Armen Kteyan, Sheldon X.-D. Tan, Valeriy Sukharev. Physics-Based Electromigration Models and Full-Chip Assessment for Power Grid Networks
    1862 -- 1875Tsung-Wei Huang, Martin D. F. Wong. UI-Timer 1.0: An Ultrafast Path-Based Timing Analysis Algorithm for CPPR
    1876 -- 1889Martin Lukasiewycz, Matthias Kauer, Sebastian Steinhorst. Synthesis of Active Cell Balancing Architectures for Battery Packs
    1890 -- 1902Xue Lin, Yanzhi Wang, Naehyuck Chang, Massoud Pedram. Concurrent Task Scheduling and Dynamic Voltage and Frequency Scaling in a Real-Time Embedded System With Energy Harvesting
    1903 -- 1913Ashok Kumar Palaniswamy, Spyros Tragoudas, Themistoklis Haniotakis. ATPG for Delay Defects in Current Mode Threshold Logic Circuits
    1914 -- 1927Zahi Moudallal, Farid N. Najm. Generating Current Budgets to Guarantee Power Grid Safety
    1928 -- 1941Antara Ain, Antonio Anastasio Bruto da Costa, Pallab Dasgupta. Feature Indented Assertions for Analog and Mixed-Signal Validation
    1942 -- 1946Debao Wei, Libao Deng, Peng Zhang, Liyan Qiao, Xiyuan Peng. NRC: A Nibble Remapping Coding Strategy for NAND Flash Reliability Extension

    Volume 35, Issue 10

    1577 -- 1590Kan Zhong, Duo Liu, Liang Liang, Xiao Zhu, Linbo Long, Yi Wang, Edwin Hsing-Mean Sha. Energy-Efficient In-Memory Paging for Smartphones
    1591 -- 1604Razvan Nane, Vlad Mihai Sima, Christian Pilato, Jongsok Choi, Blair Fort, Andrew Canis, Yu-Ting Chen, Hsuan Hsiao, Stephen Dean Brown, Fabrizio Ferrandi, Jason Helge Anderson, Koen Bertels. A Survey and Evaluation of FPGA High-Level Synthesis Tools
    1605 -- 1617Jiatao Ding, Jiajia Chen, Chip-Hong Chang. A New Paradigm of Common Subexpression Elimination by Unification of Addition and Subtraction
    1618 -- 1629Subhendu Roy, Derong Liu, Jagmohan Singh, Junhyung Um, David Z. Pan. OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions
    1630 -- 1639Ayman Yehia Hamouda, Mohab Anis, Karim S. Karim. Model-Based Initial Bias (MIB): Toward a Single-Iteration Optical Proximity Correction
    1640 -- 1652Majid Ahadi, Sourajeet Roy. Sparse Linear Regression (SPLINER) Approach for Efficient Multidimensional Uncertainty Quantification of High-Speed Circuits
    1653 -- 1666Konstantis Daloukas, Nestor E. Evmorfopoulos, Panagiota Tsompanopoulou, George I. Stamoulis. Parallel Fast Transform-Based Preconditioners for Large-Scale Power Grid Analysis on Graphics Processing Units (GPUs)
    1667 -- 1680Gadi Oxman, Shlomo Weiss. An NoC Simulator That Supports Deflection Routing, GPU/CPU Integration, and Co-Simulation
    1681 -- 1694Hao Zhuang, Wenjian Yu, Shih-Hung Weng, Ilgweon Kang, Jeng-Hau Lin, Xiang Zhang, Ryan Coutts, Chung-Kuan Cheng. Simulation Algorithms With Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks
    1695 -- 1706Denis Oyaro, Piero Triverio. TurboMOR-RC: An Efficient Model Order Reduction Technique for RC Networks With Many Ports
    1707 -- 1720Sandeep Kumar Samal, Shreepad Panth, Kambiz Samadi, Mehdi Saedi, Yang Du, Sung Kyu Lim. Adaptive Regression-Based Thermal Modeling and Optimization for Monolithic 3-D ICs
    1721 -- 1729Yuhan Zhou, Yong Zhang, Vivek Sarin, Wangqi Qiu, Weiping Shi. Macro Model of Advanced Devices for Parasitic Extraction
    1730 -- 1743Ya-Ting Shyu, Jai-Ming Lin, Che-Chun Lin, Chun-Po Huang, Soon-Jyh Chang. An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs
    1744 -- 1754Tao Wang, Chun Zhang, Jinjun Xiong, Pei-Wen Luo, Liang-Chia Cheng, Yiyu Shi. On the Optimal Threshold Voltage Computation of On-Chip Noise Sensors
    1755 -- 1762Irith Pomeranz. Static Test Compaction for Functional Test Sequences With Restoration of Functional Switching Activity
    1763 -- 1767Wooheon Kang, Changwook Lee, Hyunyul Lim, Sungho Kang. A New 3-D Fuse Architecture to Improve Yield of 3-D Memories

    Volume 35, Issue 1

    1 -- 22Xuanyao Fong, Yusung Kim, Karthik Yogendra, Deliang Fan, Abhronil Sengupta, Anand Raghunathan, Kaushik Roy. Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives
    23 -- 36Jun Tao, Changhai Liao, Xuan Zeng, Xin Li 0001. Harvesting Design Knowledge From the Internet: High-Dimensional Performance Tradeoff Modeling for Large-Scale Analog Circuits
    37 -- 48Yu Zheng, Shuo Yang, Swarup Bhunia. SeMIA: Self-Similarity-Based IC Integrity Analysis
    49 -- 57Chongxi Bao, Domenic Forte, Ankur Srivastava. On Reverse Engineering-Based Hardware Trojan Detection
    58 -- 71Liang Shi, Kaijie Wu, Mengying Zhao, Chun Jason Xue, Duo Liu, Edwin Hsing-Mean Sha. Retention Trimming for Lifetime Improvement of Flash Memory Storage Systems
    72 -- 85Amit Kumar Singh, Muhammad Shafique, Akash Kumar, Jörg Henkel. Resource and Throughput Aware Execution Trace Analysis for Efficient Run-Time Mapping on MPSoCs
    86 -- 99Philipp Niemann, Robert Wille, D. Michael Miller, Mitchell A. Thornton, Rolf Drechsler. QMDDs: Efficient Quantum Function Representation and Manipulation
    100 -- 113Adrian Alin Lifa, Petru Eles, Zebo Peng. A Reconfigurable Framework for Performance Enhancement With Dynamic FPGA Configuration Prefetching
    114 -- 127Dimitri Kagaris. MOTO-X: A Multiple-Output Transistor-Level Synthesis CAD Tool
    128 -- 140Shyamapada Mukherjee, Suchismita Roy. Nearly-2-SAT Solutions for Segmented-Channel Routing
    141 -- 154Baris Arslan, Alex Orailoglu. Power-Aware Delay Test Quality Optimization for Multiple Frequency Domains
    155 -- 165Vikram B. Suresh, Sandip Kundu. Managing Test Coverage Uncertainty due to Random Noise in Nano-CMOS: A Case-Study on an SRAM Array
    166 -- 170Lechang Liu, Ramesh K. Pokharel. Compact Modeling of Phase-Locked Loop Frequency Synthesizer for Transient Phase Noise and Jitter Simulation
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