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214 | -- | 226 | Florian Sagstetter, Martin Lukasiewycz, Samarjit Chakraborty. Generalized Asynchronous Time-Triggered Scheduling for FlexRay |
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241 | -- | 254 | Rui Wang, Dan Jia, Tao Li, Depei Qian. Achieving Versatile and Simultaneous Cache Optimizations With Nonvolatile SRAM |
255 | -- | 264 | Xiaodao Chen, Dongmei Zhang, Lizhe Wang, Ning Jia, Zhijiang Kang, Yun Zhang, Shiyan Hu. Design Automation for Interwell Connectivity Estimation in Petroleum Cyber-Physical Systems |
265 | -- | 278 | Arash Saifhashemi, Hsin-Ho Huang, Peter A. Beerel. Reconditioning: A Framework for Automatic Power Optimization of QDI Circuits |
279 | -- | 284 | Qiao Chen, Xiaoping Wang, Haibo Wan, Ran Yang. A Logic Circuit Design for Perfecting Memristor-Based Material Implication |
285 | -- | 298 | Changlin Chen, Yaowen Fu, Sorin Cotofana. Towards Maximum Utilization of Remained Bandwidth in Defected NoC Links |
299 | -- | 312 | Zhuoran Zhao, Andreas Gerstlauer, Lizy K. John. Source-Level Performance, Energy, Reliability, Power and Thermal (PERPT) Simulation |
313 | -- | 324 | Xin Lou, Ya Jun Yu, Pramod Kumar Meher. Lower Bound Analysis and Perturbation of Critical Path for Area-Time Efficient Multiple Constant Multiplications |
325 | -- | 335 | Ahish Mysore Somashekar, Spyros Tragoudas. Diagnosis of Performance Limiting Segments in Integrated Circuits Using Path Delay Measurements |
336 | -- | 345 | Jaeseok Park, Hyunyul Lim, Sungho Kang. FRESH: A New Test Result Extraction Scheme for Fast TSV Tests |
346 | -- | 350 | Liheng Zhu, Yasmine Badr, Shaodi Wang, Subramanian Iyer, Puneet Gupta. Assessing Benefits of a Buried Interconnect Layer in Digital Designs |
351 | -- | 355 | Irith Pomeranz. Sequential Test Generation Based on Preferred Primary Input Cubes |