0 | -- | 0 | Martin Palkovic, Francky Catthoor, Henk Corporaal. Trade-offs in loop transformations |
0 | -- | 0 | Yu-Ru Hong, Juinn-Dar Huang. Reducing fault dictionary size for million-gate large circuits |
0 | -- | 0 | Rajdeep Mukhopadhyay, S. K. Panda, Pallab Dasgupta, John Gough. Instrumenting AMS assertion verification on commercial platforms |
0 | -- | 0 | Sudeep Pasricha, Young-Hwan Park, Nikil D. Dutt, Fadi J. Kurdahi. System-level PVT variation-aware power exploration of on-chip communication architectures |
0 | -- | 0 | Meikang Qiu, Edwin Hsing-Mean Sha. Cost minimization while satisfying hard/soft timing constraints for heterogeneous embedded systems |
0 | -- | 0 | Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan. BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability |
0 | -- | 0 | Franco Fummi, Mirko Loghi, Massimo Poncino, Graziano Pravadelli. A cosimulation methodology for HW/SW validation and performance estimation |
0 | -- | 0 | Yokesh Kumar, Prosenjit Gupta. External memory layout vs. schematic |
0 | -- | 0 | Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang. Skew-aware polarity assignment in clock tree |
0 | -- | 0 | Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos. Efficient partial scan cell gating for low-power scan-based testing |
0 | -- | 0 | Daler N. Rakhmatov. Battery voltage modeling for portable systems |
0 | -- | 0 | Karin Avnit, Vijay D Silva, Arcot Sowmya, S. Ramesh, Sri Parameswaran. Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis |
0 | -- | 0 | Xiangrong Zhou, Chenjie Yu, Peter Petrov. Temperature-aware register reallocation for register file power-density minimization |
0 | -- | 0 | Hiroaki Inoue, Tsuyoshi Abe, Kazuhisa Ishizaka, Junji Sakai, Masato Edahiro. Dynamic security domain scaling on embedded symmetric multiprocessors |
0 | -- | 0 | Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas. FPGA-based hardware acceleration for Boolean satisfiability |