Journal: ACM Trans. Design Autom. Electr. Syst.

Volume 14, Issue 4

0 -- 0Nagarajan Ranganathan, Upavan Gupta, Venkataraman Mahalingam. Variation-aware multimetric optimization during gate sizing
0 -- 0ByungHyun Lee, Ki-Seok Chung, Bontae Koo, Nak-Woong Eum, Taewhan Kim. Thermal sensor allocation and placement for reconfigurable systems
0 -- 0Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin. Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs
0 -- 0Sivaram Gopalakrishnan, Priyank Kalla. 2009 ACM TODAES best paper award: Optimization of polynomial datapaths using finite ring algebra
0 -- 0Piet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian. SUPERB: Simulator utilizing parallel evaluation of resistive bridges
0 -- 0Po-Yuan Chen, Chiao-Chen Fang, TingTing Hwang, Hsi-Pin Ma. Leakage reduction, delay compensation using partition-based tunable body-biasing techniques
0 -- 0Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang. T-trees: A tree-based representation for temporal and three-dimensional floorplanning
0 -- 0Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer. Power-delay optimization in VLSI microprocessors by wire spacing
0 -- 0Peter Bertels, Wim Heirman, Erik H. D Hollander, Dirk Stroobandt. Efficient memory management for hardware accelerated Java Virtual Machines
0 -- 0Miad Faezipour, Mehrdad Nourani, Rina Panigrahy. A hardware platform for efficient worm outbreak detection

Volume 14, Issue 3

0 -- 0Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung. Word-length selection for power minimization via nonlinear optimization
0 -- 0Tan Yan, Martin D. F. Wong. Theories and algorithms on single-detour routing for untangling twisted bus
0 -- 0Praveen Raghavan, Murali Jayapala, Andy Lambrechts, Javed Absar, Francky Catthoor. Playing the trade-off game: Architecture exploration using Coffeee
0 -- 0Chih-Hung Liu, Shih-Yi Yuan, Sy-Yen Kuo, Szu-Chi Wang. High-performance obstacle-avoiding rectilinear steiner tree construction
0 -- 0Bo Liu, Francisco V. Fernández, Georges G. E. Gielen, R. Castro-López, Elisenda Roca. A memetic approach to the automatic design of high-performance analog integrated circuits
0 -- 0Madhu Mutyam. Selective shielding technique to eliminate crosstalk transitions
0 -- 0Pedro Marques Morgado, Paulo F. Flores, L. Miguel Silveira. Generating realistic stimuli for accurate power grid analysis
0 -- 0Philippe Grosse, Yves Durand, Paul Feautrier. Methods for power optimization in SOC-based data flow systems
0 -- 0Jason Cong, Yiping Fan, Junjuan Xu. Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture
0 -- 0Baris Taskin, Joseph Demaio, Owen Farell, Michael Hazeltine, Ryan Ketner. Custom topology rotary clock router with tree subnetworks
0 -- 0Dipankar Das, P. P. Chakrabarti, Rajeev Kumar. Scenario-based timing verification of multiprocessor embedded applications
0 -- 0Hao Yu, Joanna Ho, Lei He. Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity
0 -- 0Avinash Malik, Zoran A. Salcic, Partha S. Roop. SystemJ compilation using the tandem virtual machine approach

Volume 14, Issue 2

0 -- 0Martin Palkovic, Francky Catthoor, Henk Corporaal. Trade-offs in loop transformations
0 -- 0Yu-Ru Hong, Juinn-Dar Huang. Reducing fault dictionary size for million-gate large circuits
0 -- 0Rajdeep Mukhopadhyay, S. K. Panda, Pallab Dasgupta, John Gough. Instrumenting AMS assertion verification on commercial platforms
0 -- 0Sudeep Pasricha, Young-Hwan Park, Nikil D. Dutt, Fadi J. Kurdahi. System-level PVT variation-aware power exploration of on-chip communication architectures
0 -- 0Meikang Qiu, Edwin Hsing-Mean Sha. Cost minimization while satisfying hard/soft timing constraints for heterogeneous embedded systems
0 -- 0Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan. BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability
0 -- 0Franco Fummi, Mirko Loghi, Massimo Poncino, Graziano Pravadelli. A cosimulation methodology for HW/SW validation and performance estimation
0 -- 0Yokesh Kumar, Prosenjit Gupta. External memory layout vs. schematic
0 -- 0Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang. Skew-aware polarity assignment in clock tree
0 -- 0Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos. Efficient partial scan cell gating for low-power scan-based testing
0 -- 0Daler N. Rakhmatov. Battery voltage modeling for portable systems
0 -- 0Karin Avnit, Vijay D Silva, Arcot Sowmya, S. Ramesh, Sri Parameswaran. Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis
0 -- 0Xiangrong Zhou, Chenjie Yu, Peter Petrov. Temperature-aware register reallocation for register file power-density minimization
0 -- 0Hiroaki Inoue, Tsuyoshi Abe, Kazuhisa Ishizaka, Junji Sakai, Masato Edahiro. Dynamic security domain scaling on embedded symmetric multiprocessors
0 -- 0Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas. FPGA-based hardware acceleration for Boolean satisfiability

Volume 14, Issue 1

0 -- 0Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh. Opposite-phase register switching for peak current minimization
0 -- 0Zijiang Yang, Chao Wang, Aarti Gupta, Franjo Ivancic. Model checking sequential software programs via mixed symbolic analysis
0 -- 0Andreas Hansson, Kees Goossens, Marco Bekooij, Jos Huisken. CoMPSoC: A template for composable and predictable multi-processor system on chips
0 -- 0Yen-Chun Lin, Li-Ling Hung. Straightforward construction of depth-size optimal, parallel prefix circuits with fan-out 2
0 -- 0Pedro Reviriego, Juan Antonio Maestro. Efficient error detection codes for multiple-bit upset correction in SRAMs with BICS
0 -- 0Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang. Lens aberration aware placement for timing yield
0 -- 0Chiu-Wing Sham, Evangeline F. Y. Young, Jingwei Lu. Congestion prediction in early stages of physical design
0 -- 0Chih-Da Chien, Cheng-An Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng. A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications
0 -- 0Stefan Valentin Gheorghita, Martin Palkovic, Juan Hamers, Arnout Vandecappelle, Stelios Mamagkakis, Twan Basten, Lieven Eeckhout, Henk Corporaal, Francky Catthoor, Frederik Vandeputte, Koen De Bosschere. System-scenario-based design of dynamic embedded systems
0 -- 0Arnab Sinha, Pallab Dasgupta, Bhaskar Pal, Sayantan Das, Prasenjit Basu, P. P. Chakrabarti. Design intent coverage revisited
0 -- 0Gayatri Mehta, Justin Stander, Mustafa Baz, Brady Hunsaker, Alex K. Jones. Interconnect customization for a hardware fabric
0 -- 0Ali Dasdan. Provably efficient algorithms for resolving temporal and spatial difference constraint violations
0 -- 0Qiang Xu, Yubin Zhang, Krishnendu Chakrabarty. SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects
0 -- 0Chin-Hsien Wu. An energy-efficient I/O request mechanism for multi-bank flash-memory storage systems
0 -- 0Joachim Keinert, Martin Streubühr, Thomas Schlichter, Joachim Falk, Jens Gladigau, Christian Haubelt, Jürgen Teich, Michael Meredith. SystemCoDesigner—an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications
0 -- 0Zhong-Yi Jin, Curt Schurgers, Rajesh K. Gupta. A gateway node with duty-cycled radio and processing subsystems for wireless sensor networks
0 -- 0Yi Zhu, Yuanfang Hu, Michael Bedford Taylor, Chung-Kuan Cheng. Energy and switch area optimizations for FPGA global routing architectures
0 -- 0Swapna R. Dontharaju, Shen Chih Tung, James T. Cain, Leonid Mats, Marlin H. Mickle, Alex K. Jones. A design automation and power estimation flow for RFID systems