0 | -- | 0 | Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung. Word-length selection for power minimization via nonlinear optimization |
0 | -- | 0 | Tan Yan, Martin D. F. Wong. Theories and algorithms on single-detour routing for untangling twisted bus |
0 | -- | 0 | Praveen Raghavan, Murali Jayapala, Andy Lambrechts, Javed Absar, Francky Catthoor. Playing the trade-off game: Architecture exploration using Coffeee |
0 | -- | 0 | Chih-Hung Liu, Shih-Yi Yuan, Sy-Yen Kuo, Szu-Chi Wang. High-performance obstacle-avoiding rectilinear steiner tree construction |
0 | -- | 0 | Bo Liu, Francisco V. Fernández, Georges G. E. Gielen, R. Castro-López, Elisenda Roca. A memetic approach to the automatic design of high-performance analog integrated circuits |
0 | -- | 0 | Madhu Mutyam. Selective shielding technique to eliminate crosstalk transitions |
0 | -- | 0 | Pedro Marques Morgado, Paulo F. Flores, L. Miguel Silveira. Generating realistic stimuli for accurate power grid analysis |
0 | -- | 0 | Philippe Grosse, Yves Durand, Paul Feautrier. Methods for power optimization in SOC-based data flow systems |
0 | -- | 0 | Jason Cong, Yiping Fan, Junjuan Xu. Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture |
0 | -- | 0 | Baris Taskin, Joseph Demaio, Owen Farell, Michael Hazeltine, Ryan Ketner. Custom topology rotary clock router with tree subnetworks |
0 | -- | 0 | Dipankar Das, P. P. Chakrabarti, Rajeev Kumar. Scenario-based timing verification of multiprocessor embedded applications |
0 | -- | 0 | Hao Yu, Joanna Ho, Lei He. Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity |
0 | -- | 0 | Avinash Malik, Zoran A. Salcic, Partha S. Roop. SystemJ compilation using the tandem virtual machine approach |