| 17 | -- | 0 | Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis Jen-Hsin Huang, Chin-Chi Teng, Chung-Kuan Cheng. ePlace: Electrostatics-Based Placement Using Fast Fourier Transform and Nesterov's Method |
| 18 | -- | 0 | Qi Guo, Tianshi Chen, Zhi-Hua Zhou, Olivier Temam, Ling Li, Depei Qian, Yunji Chen. Robust Design Space Modeling |
| 19 | -- | 0 | Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen. Yield Improvement for 3D Wafer-to-Wafer Stacked ICs Using Wafer Matching |
| 20 | -- | 0 | Naiwen Chang, Eddie Cheng, Sunyuan Hsieh. Conditional Diagnosability of Cayley Graphs Generated by Transposition Trees under the PMC Model |
| 21 | -- | 0 | Qing Duan, Jun Zeng, Krishnendu Chakrabarty, Gary Dispoto. Data-Driven Optimization of Order Admission Policies in a Digital Print Factory |
| 22 | -- | 0 | Cheng-Yen Lin, Chung-Wen Huang, Chi-Bang Kuan, Shi-Yu Huang, Jenq Kuen Lee. The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multicore Systems |
| 23 | -- | 0 | Marjan Asadinia, Mohammad Arjomand, Hamid Sarbazi-Azad. Prolonging Lifetime of PCM-Based Main Memories through On-Demand Page Pairing |
| 24 | -- | 0 | Xing Huang, Genggeng Liu, Wenzhong Guo, Yuzhen Niu, Guolong Chen. Obstacle-Avoiding Algorithm in X-Architecture Based on Discrete Particle Swarm Optimization for VLSI Design |
| 25 | -- | 0 | Hung-Sheng Chang, Yuan-Hao Chang, Pi-Cheng Hsiu, Tei-Wei Kuo, Hsiang-Pang Li. Marching-Based Wear-Leveling for PCM-Based Storage Systems |
| 26 | -- | 0 | Gang Chen, Kai Huang 0001, Christian Buckl, Alois Knoll. Applying Pay-Burst-Only-Once Principle for Periodic Power Management in Hard Real-Time Pipelined Multiprocessor Systems |
| 27 | -- | 0 | Franck Yonga, Michael Mefenza, Christophe Bobda. ASP-Based Encoding Model of Architecture Synthesis for Smart Cameras in Distributed Networks |
| 28 | -- | 0 | Lok-Won Kim, Dong-U Lee, John D. Villasenor. Automated Iterative Pipelining for ASIC Design |
| 29 | -- | 0 | Irith Pomeranz. A Generalized Definition of Unnecessary Test Vectors in Functional Test Sequences |
| 30 | -- | 0 | Rafal Baranowski, Michael A. Kochte, Hans-Joachim Wunderlich. Reconfigurable Scan Networks: Modeling, Verification, and Optimal Pattern Generation |
| 31 | -- | 0 | Kamel Beznia, Ahcène Bounceur, Reinhardt Euler, Salvador Mir. A Tool for Analog/RF BIST Evaluation Using Statistical Models of Circuit Parameters |
| 32 | -- | 0 | Adwait Gupte, Sudhanshu Vyas, Phillip H. Jones. A Fault-Aware Toolchain Approach for FPGA Fault Tolerance |
| 33 | -- | 0 | Jiliang Zhang, Yaping Lin, Gang Qu. Reconfigurable Binding against FPGA Replay Attacks |