| 265 | -- | 266 | Mary Jane Irwin. Editorial |
| 267 | -- | 293 | R. Iris Bahar, Ernest T. Lampe, Enrico Macii. Power optimization of technology-dependent circuits based on symbolic computation of logic implications |
| 294 | -- | 310 | M. Balakrishnan, Heman Khanna. Allocation of FIFO structures in RTL data paths |
| 311 | -- | 321 | Luca Benini, Giovanni De Micheli. Synthesis of low-power selectively-clocked systems from high-level specification |
| 322 | -- | 336 | Stephen A. Blythe, Robert A. Walker. Efficient optimal design space characterization methodologies |
| 337 | -- | 372 | Alessandro Bogliolo, Luca Benini, Giovanni De Micheli. Regression-based RTL power modeling |
| 373 | -- | 398 | Surendra Bommu, Niall O Neill, Maciej J. Ciesielski. Retiming-based factorization for sequential logic optimization |
| 399 | -- | 432 | Vincenza Carchiolo, Michele Malgeri, Giuseppe Mangioni. Hardware/software synthesis of formal specifications in codesign of embedded systems |
| 433 | -- | 450 | Yao-Wen Chang, Kai Zhu, D. F. Wong. Timing-driven routing for symmetrical array-based FPGAs |
| 451 | -- | 491 | Donald S. Gelosh, Dorothy E. Setliff. Modeling layout tools to derive forward estimates of area and delay at the RTL level |
| 492 | -- | 509 | Guy Gogniat, Michel Auguin, Luc Bianco, Alain Pegatoquet. A codesign back-end approach for embedded system design |
| 510 | -- | 547 | Avaneendra Gupta, John P. Hayes. CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells |
| 548 | -- | 565 | Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel. Dynamic state traversal for sequential circuit test generation |
| 566 | -- | 603 | Pradip K. Jha, Nikil D. Dutt. High-level library mapping for memories |
| 604 | -- | 630 | Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak. Optimizing computations for effective block-processing |
| 631 | -- | 657 | David E. Long, Mahesh A. Iyer, Miron Abramovici. FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults |
| 658 | -- | 681 | Diana Marculescu, Radu Marculescu, Massoud Pedram. Stochastic sequential machine synthesis with application to constrained sequence generation |
| 682 | -- | 704 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau. On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems |
| 705 | -- | 725 | Richard Raimi, Ramin Hojati, Kedar S. Namjoshi. Environment modeling and language universality |
| 726 | -- | 734 | Jin-Tai Yan. Three-layer bubble-sorting-based nonManhattan channel routing |
| 735 | -- | 747 | Cheng-Hsing Yang, Sao-Jie Chen, Jan-Ming Ho, Chia-Chun Tsai. Efficient routability check algorithms for segmented channel routing |