Journal: TRETS

Volume 11, Issue 4

0 -- 0Naveen Kumar Dumpala, Shivukumar B. Patil, Daniel Holcomb, Russell Tessier. Loop Unrolling for Energy Efficiency in Low-Cost Field-Programmable Gate Arrays
0 -- 0Alexander Kroh, Oliver Diessel. Efficient Fine-grained Processor-logic Interactions on the Cache-coherent Zynq Platform
0 -- 0Haomiao Wang, Prabu Thiagaraj, Oliver Sinnen. FPGA-based Acceleration of FT Convolution for Pulsar Search Using OpenCL
0 -- 0Gai Liu, Zhiru Zhang. PIMap: A Flexible Framework for Improving LUT-Based Technology Mapping via Parallelized Iterative Optimization

Volume 11, Issue 3

0 -- 0Jincheng Yu, Guangjun Ge, Yiming Hu, Xuefei Ning, Jiantao Qiu, Kaiyuan Guo, Yu Wang, Huazhong Yang. Instruction Driven Cross-layer CNN Accelerator for Fast Detection on FPGA
0 -- 0Deming Chen, Andrew Putnam, Steven J. E. Wilton. Introduction to the Special Section on Deep Learning in FPGAs
0 -- 0Shuanglong Liu, Hongxiang Fan, Xinyu Niu, Ho-Cheung Ng, Yang Chu, Wayne Luk. Optimizing CNN-based Segmentation with Deeply Customized Convolutional and Deconvolutional Architectures on FPGA
0 -- 0Adrien Prost-Boucle, Alban Bourge, Frédéric Pétrot. High-Efficiency Convolutional Ternary Neural Networks with Custom Adder Trees and Weight Compression
0 -- 0Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser, Kees A. Vissers. R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks
0 -- 0Bita Darvish Rouhani, Siam Umar Hussain, Kristin Lauter, Farinaz Koushanfar. ReDCrypt: Real-Time Privacy-Preserving Deep Learning Inference in Clouds Using FPGAs
0 -- 0Andrew Boutros, Sadegh Yazdanshenas, Vaughn Betz. You Cannot Improve What You Do not Measure: FPGA vs. ASIC Efficiency Gaps for Convolutional Neural Network Inference
0 -- 0Ruizhou Ding, Zeye Liu, R. D. (Shawn) Blanton, Diana Marculescu. Lightening the Load with Highly Accurate Storage- and Energy-Efficient LightNNs
0 -- 0Paolo Meloni, Alessandro Capotondi, Gianfranco Deriu, Michele Brian, Francesco Conti 0001, Davide Rossi, Luigi Raffo, Luca Benini. NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs

Volume 11, Issue 2

0 -- 0Marc-André Daigneault, Jean-Pierre David. Automated Synthesis of Streaming Transfer Level Hardware Designs
0 -- 0Oleg Petelin, Vaughn Betz. Wotan: Evaluating FPGA Architecture Routability without Benchmarks
0 -- 0Deshya Wijesundera, Alok Prakash, Thambipillai Srikanthan, Achintha Ihalage. Framework for Rapid Performance Estimation of Embedded Soft Core Processors
0 -- 0N. Nalla Anandakumar, M. Prem Laxman Das, Somitra Kumar Sanadhya, Mohammad S. Hashmi. Reconfigurable Hardware Architecture for Authenticated Key Agreement Protocol Over Binary Edwards Curve
0 -- 0Enrico Rossi, Marvin Damschen, Lars Bauer, Giorgio C. Buttazzo, Jörg Henkel. Preemption of the Partial Reconfiguration Process to Enable Real-Time Computing With FPGAs

Volume 11, Issue 1

0 -- 0Hans Giesen, Benjamin Gojman, Raphael Rubin, Ji Kim, André DeHon. Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP)
0 -- 0Muhammed Al Kadi, Benedikt Janßen, Jones Yudi Mori, Michael Hübner. General-Purpose Computing with Soft GPUs on FPGAs
0 -- 0James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides. KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs
0 -- 0Zhuoran Zhao, Nguyen T. H. Nguyen, Dimitris Agiakatsikas, Ganghee Lee, Ediz Cetin, Oliver Diessel. Fine-Grained Module-Based Error Recovery in FPGA-Based TMR Systems
0 -- 0Jason D. Bakos. Introduction to the Special Section on FCCM'16
0 -- 0Henry Wong, Vaughn Betz, Jonathan Rose. High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order Soft Processors
0 -- 0Rob Stewart 0001, Kirsty Duncan, Greg Michaelson, Paulo Garcia, Deepayan Bhowmik, Andrew M. Wallace. RIPL: A Parallel Image Processing Language for FPGAs
0 -- 0Farheen Fatima Khan, Andy Ye. An Evaluation on the Accuracy of the Minimum-Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures
0 -- 0Kosuke Tatsumura, Sadegh Yazdanshenas, Vaughn Betz. Enhancing FPGAs with Magnetic Tunnel Junction-Based Block RAMs