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    Journal: TRETS

    Volume 16, Issue 4

    0 -- 0Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne. Resource Sharing in Dataflow Circuits
    0 -- 0Jing Li 0073, Martin C. Herbordt. Introduction to the Special Section on FCCM 2022
    0 -- 0Guiming Wu, Qianwen He, Jiali Jiang, Zhenxiang Zhang, Yuan Zhao, Yinchao Zou, Jie Zhang, Changzheng Wei, Ying Yan 0002, Hui Zhang. Topgun: An ECC Accelerator for Private Set Intersection
    0 -- 0Paolo Ienne. Introduction to the Special Section on FPGA 2022
    0 -- 0Kenneth Liu, Alec Lu, Kartik Samtani, Zhenman Fang, Licheng Guo. CHIP-KNNv2: A Configurable and High-Performance K-Nearest Neighbors Accelerator on HBM-based FPGAs
    0 -- 0Erwei Wang, Marie Auffret, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah, James J. Davis 0001. Logic Shrinkage: Learned Connectivity Sparsification for LUT-Based Neural Networks
    0 -- 0Jianyi Cheng, Lana Josipovic, John Wickerson, George A. Constantinides. Parallelising Control Flow in Dynamic-scheduling High-level Synthesis
    0 -- 0Anouar Nechi, Lukas Groth, Saleh Mulhem, Farhad Merchant, Rainer Buchty, Mladen Berekovic. FPGA-based Deep Learning Inference Accelerators: Where Are We Standing?
    0 -- 0Yingchun Lu, Yun Yang, Rong Hu, Huaguo Liang, Maoxiang Yi, Zhengfeng Huang, Yuanming Ma, Tian Chen, Liang Yao. High-efficiency TRNG Design Based on Multi-bit Dual-ring Oscillator
    0 -- 0Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Eddie Hung, Wuxi Li, Jason Lau, Weikang Qiao, Yuze Chi, Linghao Song, Yuanlong Xiao, Alireza Kaviani, Zhiru Zhang, Jason Cong. RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration
    0 -- 0Tiancheng Xu, Scott Rixner, Alan L. Cox. An FPGA Accelerator for Genome Variant Calling
    0 -- 0Yizhao Gao, Song Wang, Hayden Kwok-Hay So. A Reconfigurable Architecture for Real-time Event-based Multi-Object Tracking
    0 -- 0Licheng Guo, Yuze Chi, Jason Lau, Linghao Song, Xingyu Tian, Moazin Khatti, Weikang Qiao, Jie Wang 0022, Ecenur Ustun, Zhenman Fang, Zhiru Zhang, Jason Cong. TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design
    0 -- 0Marcos T. Leipnitz, Gabriel L. Nazar. Constraint-Aware Multi-Technique Approximate High-Level Synthesis for FPGAs

    Volume 16, Issue 3

    0 -- 0Miriam Leeser. Artifact Evaluation for ACM TRETS Papers Submitted from the FPT Journal Track
    0 -- 0Rasha Karakchi, Jason D. Bakos. NAPOLY: A Non-deterministic Automata Processor OverLaY
    0 -- 0Christian Skubich, Peter Reichel, Marc Reichenbach. Increasing the Robustness of TERO-TRNGs Against Process Variation
    0 -- 0Reinout Corts, Nikolaos Alachiotis 0001. A Survey of Processing Systems for Phylogenetics and Population Genetics
    0 -- 0Nicolai Fiege, Peter Zipf. BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining
    0 -- 0Prajith Ramakrishnan Geethakumari, Ioannis Sourdis. Stream Aggregation with Compressed Sliding Windows
    0 -- 0Binglei Lou, David Boland, Philip H. W. Leong. fSEAD: A Composable FPGA-based Streaming Ensemble Anomaly Detection Library
    0 -- 0Aman Arora, Atharva Bhamburkar, Aatman Borda, Tanmay Anand, Rishabh Sehgal, Bagus Hanindhito, Pierre-Emmanuel Gaillardon, Jaydeep Kulkarni, Lizy K. John. CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration
    0 -- 0Pengzhou He, Tianyou Bao, Jiafeng Xie, Moeness G. Amin. FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography
    0 -- 0Alex R. Bucknall, Suhaib A. Fahmy. ZyPR: End-to-end Build Tool and Runtime Manager for Partial Reconfiguration of FPGA SoCs at the Edge
    0 -- 0Liang Chang 0002, Xin Zhao, Jun Zhou 0017. ADAS: A High Computational Utilization Dynamic Reconfigurable Hardware Accelerator for Super Resolution
    0 -- 0Zhengyuan Shi, Cheng Chen, Gangqiang Yang, Hailiang Xiong, Fudong Li 0002, Honggang Hu, Zhiguo Wan. Design Space Exploration of Galois and Fibonacci Configuration Based on Espresso Stream Cipher
    0 -- 0Carol Jingyi Li, Xiangwei Li, Binglei Lou, Craig T. Jin, David Boland, Philip H. W. Leong. Fixed-point FPGA Implementation of the FFT Accumulation Method for Real-time Cyclostationary Analysis
    0 -- 0Gaoyu Mao, Donglong Chen, Guangyan Li, Wangchen Dai, Abdurrashid Ibrahim Sanka, Çetin Kaya Koç, Ray C. C. Cheung. High-performance and Configurable SW/HW Co-design of Post-quantum Signature CRYSTALS-Dilithium
    0 -- 0HyeGang Jun, Hanchen Ye, Hyunmin Jeong, Deming Chen. AutoScaleDSE: A Scalable Design Space Exploration Engine for High-Level Synthesis
    0 -- 0Gopal Raut, Saurabh Karkun, Santosh Kumar Vishvakarma. An Empirical Approach to Enhance Performance for Scalable CORDIC-Based Deep Neural Networks
    0 -- 0Pedro Machado, João Filipe Ferreira, Andreas Oikonomou, T. M. McGinnity. NeuroHSMD: Neuromorphic Hybrid Spiking Motion Detector

    Volume 16, Issue 2

    0 -- 0Stephanie Soldavini, Karl F. A. Friebel, Mattia Tibaldi, Gerald Hempel, Jerónimo Castrillón, Christian Pilato. Automatic Creation of High-bandwidth Memory Architectures from Domain-specific Languages: The Case of Computational Fluid Dynamics
    0 -- 0Gangqiang Yang, Zhengyuan Shi, Cheng Chen, Hailiang Xiong, Fudong Li 0002, Honggang Hu, Zhiguo Wan. Hardware Optimizations of Fruit-80 Stream Cipher: Smaller than Grain
    0 -- 0Alexandre Proulx, Jean-Yves Chouinard, Paul Fortier, Amine Miled 0001. A Survey on FPGA Cybersecurity Design Strategies
    0 -- 0Tomohiro Ueno, Kentaro Sano. VCSN: Virtual Circuit-Switching Network for Flexible and Simple-to-Operate Communication in HPC FPGA Cluster
    0 -- 0Chanaka Ganewattha, Zaheer Khan 0001, Janne Lehtomäki, Matti Latva-aho. Hardware-accelerated Real-time Drift-awareness for Robust Deep Learning on Wireless RF Data
    0 -- 0Andreas Koch, Wei Zhang. Introduction to the Special Issue on FPT 2021
    0 -- 0Marius Meyer, Tobias Kenter, Christian Plessl. Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-switched Inter-FPGA Networks
    0 -- 0Young Kyu Choi, Carlos Santillana, Yujia Shen, Adnan Darwiche, Jason Cong. FPGA Acceleration of Probabilistic Sentential Decision Diagrams with High-level Synthesis
    0 -- 0Kang Zhao, Yuchun Ma, Ruining He, Jixing Zhang, Ning Xu 0006, Jinian Bian. Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow
    0 -- 0Richard Gebauer, Nick Karcher, Mehmed Güler, Oliver Sander. QiCells: A Modular RFSoC-based Approach to Interface Superconducting Quantum Bits
    0 -- 0Soheil Nazar Shahsavani, Arash Fayyazi, Mahdi Nazemi, Massoud Pedram. Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis
    0 -- 0Suhail Basalama, Atefeh Sohrabizadeh, Jie Wang 0022, Licheng Guo, Jason Cong. FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA
    0 -- 0Xingyu Tian, Zhifan Ye, Alec Lu, Licheng Guo, Yuze Chi, Zhenman Fang. SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs
    0 -- 0Ankita Nayak, Keyi Zhang, Rajsekhar Setaluri, Alex Carsello, Makai Mann, Christopher Torng, Stephen Richardson, Rick Bahr, Pat Hanrahan, Mark Horowitz, Priyanka Raina. Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains
    0 -- 0Dhayalakumar M, Sk. Noor Mahammad. Deterministic Approach for Range-enhanced Reconfigurable Packet Classification Engine
    0 -- 0Sameh Attia, Vaughn Betz. Toward Software-like Debugging for FPGAs via Checkpointing and Transaction-based Co-Simulation
    0 -- 0Han-Sok Suh, Jian Meng, Ty Nguyen, Vijay Kumar 0001, Yu Cao 0001, Jae-sun Seo. Algorithm-hardware Co-optimization for Energy-efficient Drone Detection on Resource-constrained FPGA

    Volume 16, Issue 1

    0 -- 0Amin Kalantar, Zachary Zimmerman, Philip Brisk. FPGA-based Acceleration of Time Series Similarity Prediction: From Cloud to Edge
    0 -- 0Ilias Giechaskiel, Shanquan Tian, Jakub Szefer. Cross-VM Covert- and Side-Channel Attacks in Cloud FPGAs
    0 -- 0Riadh Ben Abdelhamid, Yoshiki Yamaguchi, Taisuke Boku. A Scalable Many-core Overlay Architecture on an HBM2-enabled Multi-Die FPGA
    0 -- 0Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, He Li 0008, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk. Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks
    0 -- 0Oliver Sinnen, Qiang Liu 0011, Azadeh Davoodi. Introduction to Special Section on FPT'20
    0 -- 0Shayan Moini, Aleksa Deric, Xiang Li, George Provelengios, Wayne P. Burleson, Russell Tessier, Daniel E. Holcomb. Voltage Sensor Implementations for Remote Power Attacks on FPGAs
    0 -- 0Dennis Leander Wolf, Christoph Spang 0001, Daniel Diener, Christian Hochberger. Advantages of a Statistical Estimation Approach for Clock Frequency Estimation of Heterogeneous and Irregular CGRAs
    0 -- 0Zhuofu Tao, Chen Wu, Yuan Liang, Kun Wang 0005, Lei He 0001. LW-GCN: A Lightweight FPGA-based Graph Convolutional Network Accelerator
    0 -- 0Xiang Li, Peter Stanwicks, George Provelengios, Russell Tessier, Daniel E. Holcomb. Jitter-based Adaptive True Random Number Generation Circuits for FPGAs in the Cloud
    0 -- 0Niklas Schelten, Fritjof Steinert, Justin Knapheide, Anton Schulte, Benno Stabernack. A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application
    0 -- 0Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto. Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units
    0 -- 0Lenos Ioannou, Suhaib A. Fahmy. Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs
    0 -- 0Kaichuang Shi, Xuegong Zhou, Hao Zhou, Lingli Wang. An Optimized GIB Routing Architecture with Bent Wires for FPGA
    0 -- 0Xiangwei Li, Douglas L. Maskell, Carol Jingyi Li, Philip H. W. Leong, David Boland. A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation
    0 -- 0Veronia Iskandar, Mohamed A. Abd El ghany, Diana Göhringer. Near-memory Computing on FPGAs with 3D-stacked Memories: Applications, Architectures, and Optimizations
    0 -- 0Rafael Fão de Moura, João Paulo Cardoso de Lima, Luigi Carro. Data and Computation Reuse in CNNs Using Memristor TCAMs
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