| 1 | -- | 0 | Jon T. Butler, Tsutomu Sasao. High-Speed Hardware Partition Generation |
| 7 | -- | 0 | Pawel Swierczynski, Amir Moradi, David Oswald, Christof Paar. Physical Security Evaluation of the Bitstream Encryption Mechanism of Altera Stratix II and Stratix III FPGAs |
| 8 | -- | 0 | Jo Vliegen, Nele Mentens, Ingrid Verbauwhede. Secure, Remote, Dynamic Reconfiguration of FPGAs |
| 10 | -- | 0 | Bailey Miller, Frank Vahid, Tony Givargis, Philip Brisk. Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation |
| 28 | -- | 0 | Jon T. Butler, Tsutomu Sasao. High-Speed Hardware Partition Generation |
| 29 | -- | 0 | Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso. A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses |
| 30 | -- | 0 | Udit Dhawan, André DeHon. Area-Efficient Near-Associative Memories on FPGAs |
| 31 | -- | 0 | Daniel Llamocca, Marios S. Pattichis. Dynamic Energy, Performance, and Accuracy Optimization and Management Using Automatically Generated Constraints for Separable 2D FIR Filtering for Digital Video Processing |
| 32 | -- | 0 | Benjamin Gojman, Sirisha Nalmela, Nikil Mehta, Nicholas Howarth, André DeHon. GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays Using Timing Extraction |
| 33 | -- | 0 | Atabak Mahram, Martin C. Herbordt. NCBI BLASTP on High-Performance Reconfigurable Computing Systems |
| 34 | -- | 0 | Pawel Swierczynski, Amir Moradi, David Oswald, Christof Paar. Physical Security Evaluation of the Bitstream Encryption Mechanism of Altera Stratix II and Stratix III FPGAs |
| 35 | -- | 0 | Jo Vliegen, Nele Mentens, Ingrid Verbauwhede. Secure, Remote, Dynamic Reconfiguration of FPGAs |
| 36 | -- | 0 | Thomas C. P. Chau, Xinyu Niu, Alison Eele, Jan M. Maciejowski, Peter Y. K. Cheung, Wayne Luk. Mapping Adaptive Particle Filters to Heterogeneous Reconfigurable Systems |
| 37 | -- | 0 | Bailey Miller, Frank Vahid, Tony Givargis, Philip Brisk. Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation |