| 97 | -- | 110 | Girish N. Patel, Michael S. Reid, David E. Schimmel, Stephen P. DeWeerth. An asynchronous architecture for modeling intersegmental neural communication |
| 111 | -- | 121 | Orlando J. Hernandez. A high-performance VLSI architecture for the histogram peak-climbing data clustering algorithm |
| 122 | -- | 134 | Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija. Energy optimization of pipelined digital systems using circuit sizing and supply scaling |
| 135 | -- | 147 | J. Khan, R. Vemuri. Energy management for battery-powered reconfigurable computing platforms |
| 148 | -- | 160 | Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo. Low-power network-on-chip for high-performance SoC design |
| 161 | -- | 172 | Guoqing Chen, Eby G. Friedman. Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints |
| 173 | -- | 182 | Lin Yuan, Gang Qu. A combined gate replacement and input vector control approach for leakage current reduction |
| 183 | -- | 192 | Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy. A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET |
| 193 | -- | 202 | Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke. X-masking during logic BIST and its impact on defect coverage |
| 203 | -- | 207 | Dongku Kang, Hunsoo Choo, Khurram Muhammad, Kaushik Roy. Layout-driven architecture synthesis for high-speed digital filters |
| 207 | -- | 212 | Pedro Julián, Andreas G. Andreou, David H. Goldberg. A low-power correlation-derivative CMOS VLSI circuit for bearing estimation |
| 212 | -- | 213 | J. J. Rodriguez-Navarro. Comments on Carry checking/parity prediction adders and ALUs |