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    Journal: IEEE Trans. VLSI Syst.

    Volume 14, Issue 9

    925 -- 936Ming-Bo Lin, Jang-Feng Lee, Gene Eu Jan. A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture
    937 -- 950Zhongfeng Wang, Jun Ma. High-Speed Interpolation Architecture for Soft-Decision Decoding of Reed-Solomon Codes
    951 -- 961Hooman Nikmehr, Braden Phillips, Cheng-Chew Lim. Fast Decimal Floating-Point Division
    962 -- 974Minghua Shi, Amine Bermak. An Efficient Digital VLSI Implementation of Gaussian Mixture Models-Based Classifier
    975 -- 985Recep O. Ozdag, Peter A. Beerel. An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates
    986 -- 997Jason Cong, Guoling Han, Zhiru Zhang. Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors
    998 -- 1009Yajun Ran, Malgorzata Marek-Sadowska. Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics
    1010 -- 1023K. N. Vikram, V. Vasudevan. Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures
    1024 -- 1033Mehdi Baradaran Tahoori. Application-Dependent Testing of FPGAs
    1034 -- 1039Nilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi. Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis
    1039 -- 1043Madhavi Gopal Valluri, Lizy Kurian John, Heather Hanson. Hybrid-Scheduling for Reduced Energy Consumption in High-Performance Processors
    1043 -- 1047Ilya Obridko, Ran Ginosar. Minimal Energy Asynchronous Dynamic Adders

    Volume 14, Issue 8

    791 -- 801Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau. Retargetable pipeline hazard detection for partially bypassed processors
    802 -- 815Manish Verma, Peter Marwedel. Overlay techniques for scratchpad memories in low power embedded processors
    816 -- 829Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran. Exploiting statistical information for implementation of instruction scratchpad memory in embedded system
    830 -- 842Mohammad Ali Ghodrat, Tony Givargis, Alexandru Nicolau. Expression equivalence checking using interval analysis
    843 -- 853Soheil Ghiasi, Po-Kuan Huang, Roozbeh Jafari. Probabilistic delay budget assignment for synthesis of soft real-time applications
    854 -- 867Stephen A. Edwards, Olivier Tardieu. SHIM: a deterministic model for heterogeneous embedded systems
    868 -- 880JoAnn M. Paul, Donald E. Thomas, Alex Bobrek. Scenario-oriented design for single-chip heterogeneous multiprocessors
    881 -- 894Lihong Zhang, Ulrich Kleine, Yingtao Jiang. An automated design tool for analog layouts
    895 -- 905V. Chaudhary, Lawrence T. Clark. Low-power high-performance nand match line content addressable memories
    906 -- 910I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, David V. Anderson. Placement for large-scale floating-gate field-programable analog arrays
    910 -- 915Miljan Vuletic, Laura Pozzi, Paolo Ienne. Virtual memory window for application-specific reconfigurable coprocessors
    915 -- 920Jae Hyun Baek, Myung Hoon Sunwoo. New degree computationless modified euclid algorithm and architecture for Reed-Solomon decoder

    Volume 14, Issue 7

    667 -- 680Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Damien Lyonnard, Olivier Benny, Bruno Lavigueur, David Lo, Giovanni Beltrame, V. Gagne, Gabriela Nicolescu. Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia
    681 -- 692Sungchan Kim, Soonhoi Ha. Efficient exploration of bus-based system-on-chip architectures
    693 -- 706Ümit Y. Ogras, Radu Marculescu. It s a small world after all : NoC performance optimization via long-range link insertion
    707 -- 716Xinping Zhu, Wei Qin, Sharad Malik. Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation
    717 -- 729Linwei Niu, Gang Quan. Energy minimization for real-time systems with (m, k)-guarantee
    730 -- 739Juanjo Noguera, Rosa M. Badia. System-level power-performance tradeoffs for reconfigurable computing
    740 -- 753Catherine H. Gebotys. A table masking countermeasure for low-energy secure embedded systems
    754 -- 762Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne. ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors
    763 -- 776Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman. Extraction error modeling and automated model debugging in high-performance custom designs
    777 -- 779Denis Deschacht. DSM interconnects: importance of inductance effects and corresponding range of length
    780 -- 784Chi Ta Wu, Ang-Chih Hsieh, TingTing Hwang. Instruction buffering for nested loops in low-power design

    Volume 14, Issue 6

    561 -- 572Foster F. Dai, Charles E. Stroud, Dayu Yang. Automatic linearity and frequency response tests with built-in pattern generator and analyzer
    573 -- 586Nitin Mohan, W. Fung, Derek Wright, Manoj Sachdev. Design techniques and test methodology for low-power TCAMs
    587 -- 595Eric MacDonald, Nur A. Touba. Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits
    596 -- 608Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana. The LOTTERYBUS on-chip communication architecture
    609 -- 615Byeong Kil Lee, Lizy Kurian John, Eugene John. Architectural enhancements for network congestion control applications
    616 -- 624Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh. Power minimization for dynamic PLAs
    625 -- 636Arun Kejariwal, Sumit Gupta, Alexandru Nicolau, Nikil D. Dutt, Rajesh K. Gupta. Energy efficient watermarking on mobile devices using proxy-based partitioning
    637 -- 641Masud H. Chowdhury, Yehea I. Ismail. Realistic scalability of noise in dynamic circuits
    641 -- 646Junmou Zhang, Eby G. Friedman. Crosstalk modeling for coupled RLC interconnects with application to shield insertion
    646 -- 649Chris H. Kim, Kaushik Roy, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar. A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits
    649 -- 654Sunghoon Chun, YongJoon Kim, Jung-Been Im, Sungho Kang. MICRO: a new hybrid test data compression/decompression scheme
    654 -- 659J. Balachandran, Steven Brebels, G. Carchon, M. Kuijk, Walter De Raedt, Bart Nauwelaers, Eric Beyne. Wafer-level package interconnect options
    659 -- 662Mohammed Benaissa, Wei Ming Lim. Design of flexible GF(2:::m:::) elliptic curve cryptography processors

    Volume 14, Issue 5

    441 -- 451Peng Rong, Massoud Pedram. An Analytical Model for Predicting the Remaining Battery Capacity of Lithium-Ion Batteries
    452 -- 461Massimo Alioto, Gaetano Palumbo, Massimo Poli. Energy Consumption in RC Tree Circuits
    462 -- 473Andy Ye, Jonathan Rose. Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits
    474 -- 488Andy Yan, Steven J. E. Wilton. Product-Term-Based Synthesizable Embedded Programmable Logic Cores
    489 -- 500H.-Y. Hsu, J.-C. Yeo, A.-Y. Wu. Multi-Symbol-Sliced Dynamically Reconfigurable Reed-Solomon Decoder Design Based on Unified Finite-Field Processing Element
    501 -- 513Wei Huang, Shougata Ghosh, Sivakumar Velusamy, Karthik Sankaranarayanan, Kevin Skadron, Mircea R. Stan. HotSpot: A Compact Thermal Modeling Methodology for Early-Stage VLSI Design
    514 -- 524Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh. Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance
    525 -- 536Yuan Xie, Wayne Wolf, Haris Lekatsas. Code Compression for Embedded VLIW Processors Using Variable-to-Fixed Coding
    537 -- 548Adam B. Kinsman, Scott Ollivierre, Nicola Nicolici. Diagnosis of Logic Circuits Using Compressed Deterministic Data and On-Chip Response Comparison
    549 -- 552J.-J. Kim, K. Roy. A Leakage-Tolerant Low-Swing Circuit Style in Partially Depleted Silicon-on-Insulator CMOS Technologies
    553 -- 557Eric Wong, Jacob R. Minz, Sung Kyu Lim. Multi-Objective Module Placement For 3-D System-On-Package

    Volume 14, Issue 4

    313 -- 322Byung-Do Yang, Lee-Sup Kim. A low-power ROM using single charge-sharing capacitor and hierarchical bit line
    323 -- 335Alireza Ejlali, Bashir M. Al-Hashimi, Marcus T. Schmitz, Paul M. Rosinger, Seyed Ghassem Miremadi. Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems
    336 -- 348Byonghyo Shim, Naresh R. Shanbhag. Energy-efficient soft error-tolerant digital signal processing
    349 -- 360Nacer-Eddine Zergainoh, Ludovic Tambour, Ahmed Amine Jerraya. Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation
    361 -- 369Shih-Chang Hsia, Ming-Huei Chen, Po-Shien Tsai. VLSI implementation of low-power high-quality color interpolation processor for CCD camera
    370 -- 379Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert. Toward architecture-based test-vector generation for timing verification of fast parallel multipliers
    380 -- 392Sangjin Hong, Kyoung-Su Park, Jun-Hee Mun. Design and implementation of a high-speed matrix multiplier based on word-width decomposition
    393 -- 406Kamran Farzan, David A. Johns. Coding schemes for chip-to-chip interconnect applications
    407 -- 420Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod. Linear-programming-based techniques for synthesis of network-on-chip architectures
    421 -- 425Edwin Naroska, Shanq-Jang Ruan, Uwe Schwiegelshohn. Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing
    426 -- 430Chien-Ching Lin, Y.-H. Shih, Hsie-Chia Chang, Chen-Yi Lee. A low power turbo/Viterbi decoder for 3GPP2 applications
    430 -- 435Kyeong-Sik Min, Hun-Dae Choi, H.-Y. Choi, Hiroshi Kawaguchi, Takayasu Sakurai. Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V/sub DD/ LSIs

    Volume 14, Issue 3

    217 -- 228Mikhail Popovich, Eby G. Friedman. Decoupling capacitors for multi-voltage power distribution systems
    229 -- 240Woon Kang, Yong-Bin Kim, T. Doyle. A high-efficiency fully digital synchronous buck converter power delivery system based on a finite-state machine
    241 -- 253Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane. FABSYN: floorplan-aware bus architecture synthesis
    254 -- 267Hyunchul Shin, Jin-Aeon Lee, Lee-Sup Kim. A cost-effective VLSI architecture for anisotropic texture filtering in limited memory bandwidth
    268 -- 278Mohammad J. Akhbarizadeh, Mehrdad Nourani, Deepak S. Vijayasarathi, T. Balsara. A nonredundant ternary CAM circuit for network search engines
    279 -- 291Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Adonios Thanailakis. A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck
    292 -- 304Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty. Test infrastructure design for mixed-signal SOCs with wrapped analog cores
    305 -- 309Erik Larsson, Hideo Fujiwara. System-on-chip test scheduling with reconfigurable core wrappers

    Volume 14, Issue 2

    97 -- 110Girish N. Patel, Michael S. Reid, David E. Schimmel, Stephen P. DeWeerth. An asynchronous architecture for modeling intersegmental neural communication
    111 -- 121Orlando J. Hernandez. A high-performance VLSI architecture for the histogram peak-climbing data clustering algorithm
    122 -- 134Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija. Energy optimization of pipelined digital systems using circuit sizing and supply scaling
    135 -- 147J. Khan, R. Vemuri. Energy management for battery-powered reconfigurable computing platforms
    148 -- 160Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo. Low-power network-on-chip for high-performance SoC design
    161 -- 172Guoqing Chen, Eby G. Friedman. Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints
    173 -- 182Lin Yuan, Gang Qu. A combined gate replacement and input vector control approach for leakage current reduction
    183 -- 192Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy. A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET
    193 -- 202Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke. X-masking during logic BIST and its impact on defect coverage
    203 -- 207Dongku Kang, Hunsoo Choo, Khurram Muhammad, Kaushik Roy. Layout-driven architecture synthesis for high-speed digital filters
    207 -- 212Pedro Julián, Andreas G. Andreou, David H. Goldberg. A low-power correlation-derivative CMOS VLSI circuit for bearing estimation
    212 -- 213J. J. Rodriguez-Navarro. Comments on Carry checking/parity prediction adders and ALUs

    Volume 14, Issue 12

    1295 -- 1308Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors
    1309 -- 1321Sumeer Goel, Ashok Kumar, Magdy A. Bayoumi. Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style
    1322 -- 1335Massimo Alioto, Gaetano Palumbo. Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison
    1336 -- 1346Mark M. Budnik, Kaushik Roy. A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies
    1347 -- 1353Erik J. Mentze, Herbert L. Hess, Kevin M. Buck, T. G. Windley. A Scalable High-Voltage Output Driver for Low-Voltage CMOS Technologies
    1354 -- 1367Kambiz Rahimi, Chris Diorio. Design and Application of Adaptive Delay Sequential Elements
    1368 -- 1378Ming Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, N. J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, S. J. Patel. Sequential Element Design With Built-In Soft Error Resilience
    1379 -- 1383C. K. Teh, M. Hamada, T. Fujita, H. Hara, N. Ikumi, Y. Oowaki. Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems
    1383 -- 1388Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Chandramouli V. Kashyap. Fast Interconnect and Gate Timing Analysis for Performance Optimization
    1388 -- 1393José Luis Imaña, Román Hermida, Francisco Tirado. Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials
    1393 -- 1397Mosin Mondal, Yehia Massoud. Accurate Loop Self Inductance Bound for Efficient Inductance Screening

    Volume 14, Issue 11

    1165 -- 1174Rajarshi Mukherjee, Seda Ogrenci Memik. An Integrated Approach to Thermal Management in High-Level Synthesis
    1175 -- 1188Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. A Scalable Synthesis Methodology for Application-Specific Processors
    1189 -- 1202Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt. Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration
    1203 -- 1215Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara. Instruction-Based Self-Testing of Delay Faults in Pipelined Processors
    1216 -- 1226Haihua Yan, Adit D. Singh. A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI)
    1227 -- 1237Kedarnath J. Balakrishnan, Nur A. Touba. Improving Linear Test Data Compression
    1238 -- 1249Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo. Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories
    1250 -- 1263Jun-Cheol Park, Vincent John Mooney III. Sleepy Stack Leakage Reduction
    1264 -- 1275Chuan Lin, Jia Wang, Hai Zhou. Clustering for Processing Rate Optimization
    1276 -- 1281Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny. Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization
    1281 -- 1286Zahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan. Analysis and Implementation of Multiple-Input, Multiple-Output VBLAST Receiver From Area and Power Efficiency Perspective
    1286 -- 1290Thomas Lenart, Viktor Öwall. Architectures for Dynamic Data Scaling in 2/4/8K Pipeline FFT Cores

    Volume 14, Issue 10

    1049 -- 1062Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa. Efficient Synchronization for Embedded On-Chip Multiprocessors
    1063 -- 1074Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou. High Rate Data Synchronization in GALS SoCs
    1075 -- 1088Dongwoo Lee, David Blaauw, Dennis Sylvester. Runtime Leakage Minimization Through Probability-Aware Optimization
    1089 -- 1102K.-S. Hsiao, C.-H. Chen. Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation
    1103 -- 1116Ali Iranli, Wonbok Lee, Massoud Pedram. HVS-Aware Dynamic Backlight Scaling in TFT-LCDs
    1117 -- 1129Luis Alejandro Cortés, Petru Eles, Zebo Peng. Quasi-Static Assignment of Voltages and Optional Cycles in Imprecise-Computation Systems With Energy Considerations
    1130 -- 1139Thara Rejimon, Sanjukta Bhanja. A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis
    1140 -- 1146Debjit Sinha, Narendra V. Shenoy, Hai Zhou. Statistical Timing Yield Optimization by Gate Sizing
    1147 -- 1151Zhiyong He, Paul Fortier, Sébastien Roy. Highly-Parallel Decoding Architectures for Convolutional Turbo Codes
    1151 -- 1156Mohammad Maymandi-Nejad, Manoj Sachdev. DTMOS Technique for Low-Voltage Analog Circuits
    1156 -- 1161X. Zhang. Reduced Complexity Interpolation Architecture for Soft-Decision Reed–Solomon Decoding

    Volume 14, Issue 1

    1 -- 14Yajun Ran, Malgorzata Marek-Sadowska. Designing via-configurable logic blocks for regular fabric
    15 -- 22Amine Bermak, Yat-Fong Yung. A DPS array with programmable resolution and reconfigurable conversion time
    23 -- 33Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man. SWAN: high-level simulation methodology for digital substrate noise generation
    34 -- 42Shyue-Kung Lu, Yu-Chen Tsai, Chih-Hsien Hsu, Kuo-Hua Wang, Cheng-Wen Wu. Efficient built-in redundancy analysis for embedded memories with 2-D redundancy
    43 -- 56Y. Eslami, Ali Sheikholeslami, P. Glenn Gulak, S. Masui, K. Mukaida. An area-efficient universal cryptography processor for smart cards
    57 -- 68Ali Habibi, Sofiène Tahar. Design and verification of SystemC transaction-level models
    69 -- 80Praveen Kalla, Xiaobo Sharon Hu, Jörg Henkel. Distance-based recent use (DRU): an enhancement to instruction cache replacement policies for transition energy reduction
    81 -- 85Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu. A power-driven multiplication instruction-set design method for ASIPs
    86 -- 90Yuming Zhu, L. Li, C. Chakrabarti. Study of energy and performance of space-time decoding systems in concatenation with turbo decoding
    91 -- 94Sagar S. Sabade, D. M. H. Walker. Estimation of fault-free leakage current using wafer-level spatial information
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