| 1665 | -- | 1678 | Woosik Jeong, Ilkwon Kang, Kyowon Jin, Sungho Kang. A Fast Built-in Redundancy Analysis for Memories With Optimal Repair Rate Using a Line-Based Search Tree |
| 1679 | -- | 1690 | Keith A. Bowman, Alaa R. Alameldeen, Srikanth T. Srinivasan, Chris Wilkerson. Impact of Die-to-Die and Within-Die Parameter Variations on the Clock Frequency and Throughput of Multi-Core Processors |
| 1691 | -- | 1697 | Byeong Kil Lee, Lizy K. John. Hardware Acceleration for Media/Transaction Applications in Network Processors |
| 1698 | -- | 1708 | Shu-Yu Jiang, Kuo-Hsing Cheng, Pei-Yi Jian. A 2.5-GHz Built-in Jitter Measurement System in a Serial-Link Transceiver |
| 1709 | -- | 1718 | Chun Hok Ho, Chi Wai Yu, Philip Leong, Wayne Luk, Steven J. E. Wilton. Floating-Point FPGA: Architecture and Modeling |
| 1719 | -- | 1729 | Andrea Ricci, Matteo Grisanti, Ilaria De Munari, Paolo Ciampolini. Improved Pervasive Sensing With RFID: An Ultra-Low Power Baseband Processor for UHF Tags |
| 1730 | -- | 1741 | Sudarshan Bahukudumbi, Krishnendu Chakrabarty. Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In |
| 1742 | -- | 1748 | Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski. A Low-Power, Fast Acquisition, Data Recovery Circuit With Digital Threshold Decision for SFI-5 Application |
| 1749 | -- | 1752 | Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh. Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies |