| 1173 | -- | 1186 | Lei Zhang 0008, Yinhe Han, Qiang Xu, Xiaowei Li, Huawei Li. On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems |
| 1187 | -- | 1195 | Shah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev. An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs |
| 1196 | -- | 1202 | Peiyi Zhao, Jason McNeely, Pradeep Kumar Golconda, Soujanya Venigalla, Nan Wang, Magdy A. Bayoumi, Weidong Kuang, Luke Downey. Low-Power Clocked-Pseudo-NMOS Flip-Flop for Level Conversion in Dual Supply Systems |
| 1203 | -- | 1211 | Jie Gu, Hanyong Eom, John Keane, Chris H. Kim. Sleep Transistor Sizing and Adaptive Control for Supply Noise Minimization Considering Resonance |
| 1212 | -- | 1219 | Po-Chun Hsieh, Jing-Siang Jhuang, Pei-Yun Tsai, Tzi-Dar Chiueh. A Low-Power Delay Buffer Using Gated Driver Tree |
| 1220 | -- | 1232 | Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey. Variation-Tolerant Dynamic Power Management at the System-Level |
| 1233 | -- | 1246 | Magnus Själander, Per Larsson-Edefors. Multiplication Acceleration Through Twin Precision |
| 1247 | -- | 1259 | Julio A. de Oliveira Filho, Stephan Masekowsky, Thomas Schweizer, Wolfgang Rosenstiel. CGADL: An Architecture Description Language for Coarse-Grained Reconfigurable Arrays |
| 1260 | -- | 1266 | Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, Hoi-Jun Yoo. A 152-mW Mobile Multimedia SoC With Fully Programmable 3-D Graphics and MPEG4/H.264/JPEG |
| 1267 | -- | 1274 | Liang Zhang, J. M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon. A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling |
| 1275 | -- | 1284 | Pei-Yin Chen, Chih-Yuan Lien, Chi-Pin Lu. VLSI Implementation of an Edge-Oriented Image Scaling Processor |
| 1285 | -- | 1296 | Takahisa Wada, Shunichi Ishiwata, Katsuyuki Kimura, Keiri Nakanishi, Masato Sumiyoshi, Takashi Miyamori, Masaki Nakagawa. A VLIW Vector Media Coprocessor With Cascaded SIMD ALUs |
| 1297 | -- | 1303 | Ming-Bo Lin, Yung-Yi Chang. A New Architecture of a Two-Stage Lossless Data Compression and Decompression Algorithm |
| 1304 | -- | 1317 | Florin Balasa, Hongwei Zhu, Ilie I. Luican. Signal Assignment to Hierarchical Memory Organizations for Embedded Multidimensional Signal Processing Systems |
| 1318 | -- | 1329 | Jason Cong, Karthik Gururaj, Guoling Han, Wei Jiang. Synthesis Algorithm for Application-Specific Homogeneous Processor Networks |
| 1330 | -- | 1334 | De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang. Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing |
| 1334 | -- | 1339 | Bradley R. Quinton, Steven J. E. Wilton. Programmable Logic Core Enhancements for High-Speed On-Chip Interfaces |
| 1339 | -- | 1342 | Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos. Design of Parasitic and Process-Variation Aware Nano-CMOS RF Circuits: A VCO Case Study |
| 1343 | -- | 1347 | Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil D. Dutt, Nalini Venkatasubramanian. Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications |
| 1348 | -- | 1352 | Xianwu Xing, Ching-Chuen Jong. Multivoltage Multifrequency Low-Energy Synthesis for Functionally Pipelined Datapath |
| 1353 | -- | 1357 | Jason Thong, Nicola Nicolici. Time-Efficient Single Constant Multiplication Based on Overlapping Digit Patterns |
| 1357 | -- | 1362 | Sherief Reda, Gregory Smith 0002, Larry Smith 0004. Maximizing the Functional Yield of Wafer-to-Wafer 3-D Integration |
| 1362 | -- | 1366 | Chenjie Yu, Peter Petrov. Low-Power Snoop Architecture for Synchronized Producer-Consumer Embedded Multiprocessing |